ADSP-2171 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

比赛名单

ADSP-2171

DSP Microcomputer

Analog Devices 

ADSP-2171/ADSP-2172/ADSP-2173

ROM Enable/Data Memory Wait State

Control Register

0x3FFE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0111111111111111

DWAIT4 DWAIT3 DWAIT2 DWAIT1 DWAIT0

ROM enable

1 = enable

0 = disable

SPORT0 Multichannel Receive Word Enable Registers

1 = Channel Enabled

0 = Channel Ignored

0x3FFA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPORT0 Multichannel Transmit Word Enable Registers

1 = Channel Enabled

0 = Channel Ignored

0x3FF8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0x3FF9

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x3FF7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPORT0 Control Register

0x3FF6

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000000

Multichannel Enable MCE

Internal Serial Clock Generation ISCLK

Receive Frame Sync Required RFSR

Receive Frame Sync Width RFSW

Multichannel Frame Delay MFD

Only If Multichannel Mode Enabled

Transmit Frame Sync Required TFSR

Transmit Frame Sync Width TFSW

ITFS Internal Transmit Frame Sync Enable

(or MCL Multichannel Length; 1 = 32 words, 0 = 24 words

Only If Multichannel Mode Enabled)

SLEN Serial Word Length

DTYPE Data Format

00 = right justify, zero-fill unused MSBs

01 = right justify, sign extend into unused MSBs

10 = compand using µ-law

11 = compand using A-law

INVRFS Invert Receive Frame Sync

INVTFS Invert Transmit Frame Sync

(or INVTDV Invert Transmit Data Valid

Only If Multichannel Mode Enabled)

IRFS Internal Receive Frame Sync Enable

Control Registers

–12–

REV. A

Share Link: