ADSP-2171 查看數據表（PDF） - Analog Devices

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ADSP-2171

DSP Microcomputer

Analog Devices 

ADSP-2171/ADSP-2172/ADSP-2173

SPORT1 SCLKDIV

Serial Clock Divide Modulus

0x3FF1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPORT1 RFSDIV

Receive Frame Sync Divide Modulus

0x3FF0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPORT1 Autobuffer Control Register

0x3FEF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000

00

XTALDIS

XTAL Pin Drive Disable

during Powerdown

1 = disabled, 0 = enabled

(disable XTAL pin when no external

crystal connected)

XTALDELAY

4096 Cycle Delay Enable

1 = delay, 0 = no delay

PDFORCE

Powerdown Force

PUCR

Powerup Context Reset Enable

1 = soft reset (context clear),

0 = resume execution

RBUF

Receive Autobuffer Enable

TBUF

Transmit Autobuffer Enable

RMREG

Receive M Register

RIREG

Receive I Register

TMREG

Transmit M Register

TIREG

Transmit I Register

HIP Data Registers

HDR5

0x3FE5

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HDR4

0x3FE4

HDR3

0x3FE3

HDR2

0x3FE2

HDR1

0x3FE1

HDR0

0x3FE0

HMASK Register

0x3FE8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000000

Host HDR5

Read

Host HDR4

Read

Host HDR3

Read

Host HDR2

Read

Host HDR1

Read

Host HDR0

Read

Interrupt Enables

1 = Enable

0 = Disable

Host HDR0

Write

Host HDR1

Write

Host HDR2

Write

Host HDR3

Write

Host HDR4

Write

Host HDR5

Write

Control Registers

–14–

REV. A

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