ADSP-2171 查看數據表（PDF） - Analog Devices

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ADSP-2171

DSP Microcomputer

Analog Devices 

ADSP-2171/ADSP-2172/ADSP-2173

ADSP-2171/ADSP-2172

Parameter

Min

Max

Unit

Interrupts and Flags

Timing Requirement:

tIFS

IRQx or FI Setup before CLKOUT Low1, 2, 3

0.25tCK + 15

ns

tIFH

IRQx or FI Hold after CLKOUT High1, 2, 3

0.25tCK

ns

Switching Characteristic:

tFOH

Flag Output Hold after CLKOUT Low4

tFOD

Flag Output Delay from CLKOUT Low4

0.5tCK – 7

ns

0.5tCK + 5

ns

NOTES

1If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)

2Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

3IRQx = IRQ0, IRQ1, and IRQ2.

4Flag Output = FL0, FL1, FL2, and FO.

CLKOUT

tFOD

FLAG

OUTPUTS

IRQ x

FI

tFOH

tIFH

tIFS

Figure 9. Interrupts and Flags

–20–

REV. A

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