M6MF16S2AVP 查看數據表（PDF） - MITSUBISHI ELECTRIC

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M6MF16S2AVP

CMOS 3.3V-ONLY FLASH MEMORY & CMOS STATIC RAM Stacked-MCP (Multi Chip Package)

MITSUBISHI ELECTRIC  

PRELIMINARY Notice

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MITSUBISHI LSIs

M6MF16S2AVP

16777216-BIT (2 M x 8-BIT)

CMOS 3.3V-ONLY FLASH MEMORY

Program Command

Program consists of data load sequence to page buffer and data

program sequence to flash memory array.

A) Start Load Page Buffer (DBH/XXH/XXH)

Writing Start Load Page Buffer command allows data load to page

buffer. DBH is written to the CUI, follwed by two write cyclle of a

certain command except for Block Erase Command(20H/D0H) and

Lock Bit Program Command(77H/D0H).

B) Sequential Load to Page Buffer (DBH/FFH/00H)

Writing Sequential Load to Page Buffer command allows 256

bytes data load to page buffer sequentially. Follwing a three -

command sequence(DBH/FFH/00H) , 256 writes cycle specifying

the address and data executes loading to page buffer. In this

mode, only A0-7 is used and A8-A20 is a don't care.

C) End Load Page Buffer (5FH/XXH/XXH)

Writing End Load Page Buffer command ends data load to page

buffer. 5FH is written to the CUI, follwed by two write cyclle of a

certain command except for Block Erase Command(20H/D0H) and

Lock Bit Program command(77H/D0H). The data of page

command is stored while Vcc power is on or until writing Page

Buffer Write to Flash command or Page Buffer Clear

command.The stored data in page buffer can be changed by data

load sequence follwed by re-start load page buffer.

D) Page Buffer Write to Flash (0EH/D0H)

Programming to flash memory array from page buffer is executed

by Page Buffer Write to Flash command. The Page Buffer Write to

Flash setup command (0EH) is witten to the CUI, followed by the

confirm commasnd (D0H). In this mode, A8-A20 is used. The

WSM controls the program pulse application and verify operation.

After programming, each page buffer is cleared to "FFH". And the

page buffer data is invaid in the suspend mode.

Basically re-program must not be done on a page which has

already programmed.

DATA PROTECTION

The Flash Memory of M6MF16S2AVP provides hardware-locking of

memory blocks. Each block has an associated nonvolatile lock-bit

which determines the lock status of the block.In addition, this flash

memory has a master Write Protect pin (WP) which prevents any

modifications to memory blocks.

When WP2# is at low, all memory blocks are locked. And when both

WP1# and WP2# are at low, this part is in read array only mode.(not

be accepted any write command)

When WP1# is at low and WP2# is at high, the memory blocks whose

lock-bits are set to "0" are locked.

When both WP1# and WP2# are at high, lock-bits can be programmed

(to "0"), all blocks can be programmed or erased regardless of the

state of the lock-bits, and lock-bits are cleared to "1" by this erase. See

the BLOCK LOCKING table on P.6 for details.

Power Supply Voltage

When the power supply voltage (Vcc) is less than 2.2V, the device is

set to the Read-only mode.

A delay time of 2 us is required before any device operation is initiated.

The delay time is measured from the time Vcc reaches Vccmin.

During power up, F-RP#=GND is recommended. Falling in Busy

status is not recommended for possibility of damaging the device.

4

May.1998 , Rev.1.2

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