MU9C8328A-RDC 查看數據表（PDF） - Music Semiconductors
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MU9C8328A-RDC Datasheet PDF : 16 Pages
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MU9C8328A Ethernet Interface
FUNCTIONAL DESCRIPTION Continued
A(3–0)
0H
0H
1H
1H
2H
2H
3H
3H
4H
4H
5H
5H
6H
6H
7H
7H
8H
8H
9H
9H
AH
AH
/WE
Resource Selected
L
Control register
H
Control register
L
Reserved
H
Status Register
L
Learn Op-Code Register
H
Learn Op-Code Register
L
Reserved
H
Associated Data Register
L
LANCAM Command Cycle with /EC LOW
H
LANCAM Command Cycle with /EC LOW
L
LANCAM Command Cycle with /EC HIGH
H
LANCAM Command Cycle with /EC HIGH
L
LANCAM Data Cycle with /EC LOW
H
LANCAM Data Cycle with /EC LOW
L
LANCAM Data Cycle with /EC HIGH
H
LANCAM Data Cycle with /EC HIGH
L
Update Op-Code Register
H
Update Op-Code Register
L
Purge Op-Code Register
H
Purge Op-Code Register
L
Time stamp Register
H
Time stamp Register
Table 1: Address Decode
Action
Write
Read
Read
Write
Read
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
SERDAT
/E
/CM
/W
/EC
/MF
/REJECT
/INT
Rev. 0.8 Draft
Preamble
DA Match Found
SA No-Match/Learn
SFD DA1 DA2 DA3 SA1 SA2 SA3 Length/Type
Data
Figure 1: Typical Network Filtering
6
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