MU9C8328A-RDC 查看數據表（PDF） - Music Semiconductors
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MU9C8328A-RDC Datasheet PDF : 16 Pages
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MU9C8328A Ethernet Interface
APPLICATIONS
Connections
Connection diagrams are shown in Figures 2, 3, and 4 for
National’s SONIC, AMD’s MACE, and Motorola’s
QUICC Ethernet controller chips. Other controller chips
that provide a serial NRZ received data port and clock
can also be used in similar fashions. The /NETRDY line
is provided for controller chips that output data on the
received data line while transmitting. If /NETRDY is
deasserted, the internal network state machine will safely
complete any current activity and then wait until
/NETRDY is asserted again before parsing another frame.
If the controller chip does not output data on the received
data line while transmitting, /NETRDY may be tied to
ground, and the MU9C8328As valid clock detector will
determine when it is time to start parsing a frame.
Initialization of the LANCAM
Before using, the MUSIC LANCAMs need to be configured
for the number of LANCAMs in a daisy chain and for the
filtering conditions in the Control and Segment Control
registers. Before configuring the LANCAMs, bit 13 in the
MU9C8328A Control register needs to be set to 0, to turn off
network filtering. Table 3 shows the steps for configuring two
LANCAMs in a daisy chain. The routine selects register 05H
in the MU9C8328A, which sends Command Write cycles to
the LANCAM. The sequence shown resets the LANCAMs,
sets the Page address for both LANCAMs in the daisy chain,
then sets the Control and Segment Control registers. If a Mask
register were needed, then the sequence would be modified to
set the Persistent destination to MR1 or MR2, use MU9C8328A
register 07H to write data into the Mask register, change the
final Control register value to 8051H or 8061H instead of 8041H
to invoke MR1 or MR2 during compares, and then resetting
L A N CA M
AM79C940
SRDCLK
SRD
TXEN
/EAM/R
/E /CM /W /EC /MF /FF
/E /CM /W /EC /MF /FF
DQ(15-0)
SERCLK
SERDAT
/NETRDY
MU9C8328A
/REJECT
SYSCLK
/RESET
/CS
/AS
/WE
A(3-0)
D(15-0)
READY
/INT
Figure 2: AMD’s MACE™ Connection Diagram
L A N CA M
DP83932
RXCo
RXDo
TXE
/PREJ
/E /CM /W /EC /MF /FF
/E /CM /W /EC /MF /FF
DQ(15-0)
SERCLK
SERDAT
/NETRDY
/REJECT
MU9C8328A
SYSCLK
/RESET
/CS
/AS
/WE
A(3-0)
D(15-0)
READY
/INT
Figure 3: National’s SONIC™ Connection Diagram
MC68160
EEST
RCLK RX RENA
RCLK RXD RENA
/RRJCT
MC68360
QUICC
L A N CA M
/E /CM /W /EC /MF /FF
/E /CM /W
SERCLK
/EC /MF /FF
SERDAT
/NETRDY
MU9C8328A
/REJECT
DQ(15-0)
SYSCLK
/RESET
/CS
/AS
/WE
A(3-0)
D(15-0)
READY
/INT
Figure 4: Motorola’s QUICC™ Connection Diagram
9
Rev. 0.8 Draft
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