ISL8510 查看數據表（PDF） - Renesas Electronics
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ISL8510 Datasheet PDF : 21 Pages
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ISL8510
amplifier. The Closed Loop Gain is constructed on the graph of
Figure 31 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
100
fZ1 fZ2 fP1 fP2
80
60
OPEN LOOP
ERROR AMP GAIN
40
20LOG
20 (R2/R1)
20LOG
0
(VIN/VOSC)
MODULATOR
-20
GAIN
-40
-60
fLC
fESR
10
100
1k
10k 100k
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 31. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A more detailed explanation of voltage mode control of a buck
regulator can be found in Tech Brief TB417, entitled “Designing
Stable Compensation Networks for Single Phase Voltage
Mode Buck Regulators.”
http://www.intersil.com/data/tb/tb417.pdf
Layout Considerations
Layout is very important in high frequency switching converter
design. With power devices switching efficiently at 500kHz, the
resulting current transitions from one device to another cause
voltage spikes across the interconnecting impedances and
parasitic circuit elements. These voltage spikes can degrade
efficiency, radiate noise into the circuit, and lead to device
overvoltage stress. Careful component layout and printed
circuit board design minimizes these voltage spikes.
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET
and is picked up by the lower MOSFET. Any parasitic
inductance in the switched current path generates a large
voltage spike during the switching interval. Careful component
selection, tight layout of the critical components, and short,
wide traces minimizes the magnitude of voltage spikes.
There are two sets of critical components in the ISL8510
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are the
FN6516 Rev 2.00
December 15, 2008
small signal components, which connect to sensitive nodes or
supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 32
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer (usually a middle layer of the PC board) for a ground
plane and make all critical component ground connections with
vias to this layer. Dedicate another solid layer as a power plane
and break this plane into smaller islands of common voltage
levels. Keep the metal runs from the PHASE terminals to the
output inductor short. The power plane should support the
input power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the phase
nodes. Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the GATE pins to the MOSFET
gates should be kept short and wide enough to easily handle
the 1A of drive current.
5V
PVCC
VIN
CBP1
ISL8510
RBP
VCC
CBP2
PHASE
PGND
VIN
CIN
L
D
COUT1
VOUT1
COMP
FB
C2
R2
C1
R1
R4
C3 R3
GND PAD
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 32. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
In order to dissipate heat generated by the internal VTT LDO,
the ground pad, pin 29, should be connected to the internal
ground plane through at least four vias. This allows the heat to
move away from the IC and also ties the pad to the ground
plane through a low impedance path.
The switching components should be placed close to the
ISL6537 first. Minimize the length of the connections between
the input capacitors, CIN, and the power switches by placing
them nearby. Position both the ceramic and bulk input
capacitors as close to the upper MOSFET drain as possible.
Position the output inductor and output capacitors between the
upper and lower MOSFETs and the load.
Page 19 of 21
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