UT62L64CSCL-70 查看數據表（PDF） - Utron Technology Inc
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UT62L64CSCL-70 Datasheet PDF : 12 Pages
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UTRON
Rev. 1.3
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
Address
tAA
Dout
tOH
Previous data valid
UT62L64C
8K X 8 BIT LOW POWER CMOS SRAM
tRC
tOH
Data Valid
READ CYCLE 2 ( CE and CE2 and OE Controlled) (1,3,4,5)
Address
CE
CE2
tRC
tAA
tACE
OE
Dout
High-Z
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Data Valid
High-Z
Notes :
1. WE is high for read cycle.
2.Device is continuously selected OE =low, CE =low, CE2=high.
3.Address must be valid prior to or coincident with CE =low, CE2=high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured± 500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ,, tOHZ is less than tOLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
P80060
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