Features
• Up to 10,000 Gate Array Equivalent Gates (up to 25,000 equivalent PLD Gates)
• Highly Predictable Performance with 100% Automatic Placeand-Route
• As Low as 9.0 ns Clock-to-Output Times (–1 Speed Grade)
• Up to 186 MHz On-Chip Performance (–1 Speed Grade)
• Up to 228 User-Programmable I/O Pins
• Four Fast, Low-Skew Clock Networks
• More than 500 Macro Functions
• Replaces up to Twenty 32 Macro-Cell CPLDs
• Replaces up to One Hundred 20-Pin PAL® Packages
• Up to 1,153 Dedicated Flip-Flops
• VQFP, TQFP, BGA, and PQFP Packages
• Nonvolatile, User Programmable
• Fully Tested Prior to Shipment
• 5.0 V and 3.3 V Versions
• Optimized for Logic Synthesis Methodologies
• Low Power CMOS Technology