Functional Description
The CY23S08 is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications.
The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 250 ps.

FEATUREs
• Zero input-output propagation delay, adjustable by capacitive load on FBK input
• Multiple configurations, see Table 2
• Multiple low-skew outputs
   — Output-output skew less than 200 ps
   — Device-device skew less than 700 ps
   — Two banks of four outputs, three-stateable by two select inputs
• 10-MHz to 133-MHz operating range
• Low jitter, less than 200 ps cycle-cycle (–1, –1H, –4)
• Advanced 0.65µ CMOS technology
• Space-saving 16-pin 150-mil SOIC/TSSOP packages
• 3.3V operation
• Spread Aware™