Functional Description
The CY7C1345 is a 3.3V 128K by 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

FEATUREs
• Supports 117-MHz microprocessor cache systems with zero wait states
• 128K by 36 common I/O
• Low Standby Power (1.65 mW, L version)
• Fast clock-to-output times
   — 7.5 ns (117-MHz version)
• Two-bit wrap-around counter supporting either interleaved or linear burst sequence
• Separate processor and controller address strobes provide direct interface with the processor and external cache controller
• Synchronous self-timed write
• Asynchronous output enable
• 3.3V I/Os
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode