Functional Description[1]
The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1M x 18 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion. The CY7C1371D/CY7C1373D is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

FEATUREs
• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports up to 133-MHz bus operations with zero wait states
    — Data is transferred on every clock
• Pin-compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow through operation
• Byte Write capability
• 3.3V/2.5V IO power supply (VDDQ)
• Fast clock-to-output times
    — 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 119-Ball BGA and 165-Ball FBGA package.
• Three chip enables for simple depth expansion
• Automatic Power down feature available using ZZ mode or CE deselect
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst Capability — linear or interleaved burst order
• Low standby power