Functional Description[1]
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

FEATUREs
• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero wait states
   — Data is transferred on every clock
• Pin-compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
   — 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• CY7C1461AV33, CY7C1463AV33 available in
   JEDEC-standard lead-free 100-pin TQFP package,
   lead-free and non-lead-free 165-ball FBGA package.
   CY7C1465AV33 available in lead-free and non-lead-free
   209-ball FBGA package
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ mode or CE deselect
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst Capability—linear or interleaved burst order
• Low standby power