SigmaRAM Family Overview
GS8170DD18/36 SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage CMOS I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

FEATUREs
• Double Data Rate Read and Write mode
• JEDEC-standard SigmaRAM™ pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V I/O supply
• Pipelined read operation
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• 2 user-programmable chip enable inputs for easy depth expansion
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices