IDT54FCT388915T 数据手册 ( 数据表 ) - Integrated Device Technology
零件编号
IDT54FCT388915T
Other PDF
no available.
PDF
page
11 Pages
File Size
111.9 kB
生产厂家
Integrated Device Technology
DESCRIPTION:
The IDT54/74FCT388915T uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock.
FEATURES:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 150MHz
• Pin and function compatible with FCT88915T, MC88915T
• 5 non-inverting outputs, one inverting output, one 2x
output, one ÷2 output; all outputs are TTL-compatible
• 3-State outputs
• Output skew < 350ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 1ns (from tPD max. spec)
• 32/–16mA drive at CMOS output voltage levels
• VCC = 3.3V ± 0.3V
• Inputs can be driven by 3.3V or 5V components
• Available in 28 pin PLCC, LCC and SSOP packages
零件编号
产品描述 (功能)
PDF
生产厂家
Low Voltage Low Skew CMOS PLL Clock Driver, 3-State ( Rev : 1997 )
Motorola => Freescale
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
Integrated Device Technology
Share Link: