GENERAL DESCRIPTION
The 128MByte (1Gb) SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containing 268,435,456 bits. Each chip is internally confi gured as a quad-bank DRAM with a synchronous interface. Each of the chip’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. The MCP also incorporates two 16-bit universal bus drivers for input control signals and addresses.

FEATURES
■ Registered for enhanced performace of bus speeds
   • 100, 125, 133MHz
■ Package:
   • 219 Plastic Ball Grid Array (PBGA), 25 x 25mm
■ Single 3.3V ±0.3V power supply
■ Fully Synchronous; all signals registered on positive edge of system clock cycle
■ Internal pipelined operation; column address can be changed every clock cycle
■ Internal banks for hiding row access/precharge
■ Programmable Burst length 1,2,4,8 or full page
■ 8,192 refresh cycles
■ Commercial, Industrial and Military Temperature Ranges
■ Organized as 16M x 64
   • User confi gureable as 2 x 16M x 32
■ Weight: WEDPN16M64VR-XB2X - 2.5 grams typical

BenefitS
■ 51% SPACE SAVINGS
■ 17% I/O Reduction
■ Reduced part count
■ Reduced trace lengths for lower parasitic capacitance
■ Glue-less connection to memory controller/PCI Bridge
■ Suitable for hi-reliability applications