FEATURES
■ Access Time of 90, 120, 150ns
■ Packaging:
    • 56 Lead, Hermetic Ceramic, 0.520" CSOP (Package 213). Fits standard 56 SSOP footprint.
■ Sector Architecture
    • 32 equal size sectors of 64KBytes per each 2Mx8 chip
    • Any combination of sectors can be erased. Also supports full chip erase.
■ Minimum 100,000 Write/Erase Cycles Minimum
■ Organized as two banks of 2Mx16; User Configurable as 4 x 2Mx8
■ Commercial, Industrial, and Military Temperature Ranges
■ 5 Volt Read and Write. 5V ± 10% Supply.
■ Low Power CMOS
■ Data Polling and Toggle Bit feature for detection of program or erase cycle completion.
■ Supports reading or programming data to a sector not being erased.
■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation, Separate Power and Ground Planes to improve noise immunity
■ RESET pin resets internal state machine to the read mode.
■ Ready/Busy (RY/BY) output for direction of program or erase cycle completion.