FEATURES
■ Access Time of 100, 120, 150ns
■ Packaging:
   • 68 Lead, 40 mm (1.560") square hermetic CQFP, 5.2 mm (0.205") high (Package 503)
■ Sector Architecture
   • 32 equal size sectors of 64KBytes per each 2Mx8 chip
   • Any combination of sectors can be erased. Also supports full chip erase.
■ 100,000 Write/Erase Cycles Minimum
■ Organized as 8Mx32
■ Commercial, Industrial, and Military Temperature Ranges
■ 5 Volt Read and Write. 5V ± 10% Supply.
■ Low Power CMOS
■ Data# Polling and Toggle Bit feature for detection of program or erase cycle completion.
■ Supports reading or programming data to a sector not being erased.
■ RESET# pin resets internal state machine to the read mode. (Not available in HIP package for WF2M32-XHX5)
■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation, Seperate Power and Ground Planes to improve noise immunity.
■ Built in Buffering.