EDI9LC644V 查看數據表（PDF） - White Electronic Designs => Micro Semi
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产品描述 (功能)
比赛名单
EDI9LC644V Datasheet PDF : 25 Pages
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EDI9LC644V
Symbol
SSCLK
SSADS
SSOE
SSWE
SSCE
SDCLK
SDCE
SDRAS
SDCAS
SDWE
Type
Input
Input
Input
Input
Input
Input
A0-16,
SDA10
Input
DQ0-31
BWE0-3
Input
Output
Input
VCC, VSS
VCCQ
Supply
Supply
OUTPUT FUNCTIONAL DESCRIPTIONS
Signal
Pulse
Pulse
Polarity
Function
Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation
Active Low to be executed by the SSRAM.
Pulse
Pulse
Pulse
Pulse
Active Low SSCE disable or enable SSRAM device operation.
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Active Low SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3.
When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the
Active Low operation to be executed by the SDRAM.
Level
Level
Address bus for SSRAM and SDRAM
A0 and A1 are the burst address inputs for the SSRAM
During a Bank Active command cycle, A0-9, SDA10 defines the row address (RA0-10) when sampled
at the rising clock edge.
—
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at
the rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge
operation at the end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and
A11 defines the bank to be precharged (low = bank A, high = bank B). If SDA10 is low,
autoprecharge is disabled.
During a Precharge command cycle, SDA10 is used in conjunction with A11 to control which bank(s)
to precharge. If SDA10 is high, both bank A and Bank B will be precharged regardless of the state of
A11. If SDA10 is low, then A11 is used to define which bank to precharge.
—
Data Input/Output are multiplexed on the same pins.
Pulse
BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM.
BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31.
Power and ground for the input buffers and the core logic.
Data base power supply pins, 3.3V (2.5V future).
3
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