EDI9LC644V 查看數據表（PDF） - White Electronic Designs => Micro Semi

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EDI9LC644V

128Kx32 SSRAM/1Mx32 SDRAM

White Electronic Designs => Micro Semi 

EDI9LC644V

CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHZ SDRAM

Frequency

125MHz (8.0ns)

100MHz (10.0ns)

83MHz (12.0ns)

CAS

Latency

3

3

2

tRC

70ns

9

7

6

(UNIT = NUMBER OF CLOCK)

tRAS

tRP

tRRD

50ns

6

5

4

20ns

3

2

2

20ns

2

2

2

tRCD

20ns

3

2

2

tCCD

10ns

1

1

1

tCDL

10ns

1

1

1

CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHZ SDRAM

Frequency

100MHz (12.0ns)

83MHz (12.0ns)

CAS

Latency

3

2

tRC

70ns

7

6

(UNIT = NUMBER OF CLOCK)

tRAS

tRP

tRRD

50ns

5

5

20ns

2

2

20ns

2

2

tRCD

20ns

2

2

tCCD

10ns

1

1

tCDL

10ns

1

1

tRDL

10ns

1

1

1

tRDL

10ns

1

1

REFRESH CYCLE PARAMETERS

Parameter

Refresh Period1,2

Symbol

tREF

Min

—

-10

Max

64

Min

—

-12

Max

64

Units

ms

NOTES:

1. 4096 cycles

2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device.

SDRAM COMMAND TRUTH TABLE

Function

SDCE

SDRAS

SDCAS

SDWE

BWE

A11

SDA10

A9-0

Notes

Mode Register Set

L

L

L

L

X

OP CODE

Auto Refresh (CBR)

L

L

L

H

X

X

X

Precharge

Single Bank

L

L

H

L

X

BA

L

2

Precharge all Banks

L

L

H

L

X

X

H

Bank Activate

L

L

H

H

X

BA

Row Address 2

Write

L

H

L

L

X

BA

L

2

Write with Auto Precharge

L

H

L

L

X

BA

H

2

Read

L

H

L

L

X

BA

L

2

Read with Auto Precharge

L

H

L

H

X

BA

H

2

Burst Termination

L

H

H

L

X

X

X

3

No Operation

L

H

H

H

X

X

X

Device Deselect

H

X

X

X

X

X

X

Data Write/Output Disable

X

X

X

X

L

X

X

4

Data Mask/Output Disable

X

X

X

X

H

X

X

4

NOTES:

1. All of the SDRAM operations are defined by states of SDCE, SDWE, SDRAS, SDCAS, and BWE0-3 at the positive rising edge of the clock.

2. Bank Select (BA), if A11 = 0 then bank A is selected, if BA = 1 then bank B is selected.

3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.

4. The BWE has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE goes high at a clock timing the data outputs are

disabled and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates, the Write

operation at the clock is prohibited (zero clock latency).

White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

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