EDI9LC644V 查看數據表（PDF） - White Electronic Designs => Micro Semi
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EDI9LC644V Datasheet PDF : 25 Pages
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EDI9LC644V
SDRAM AC CHARACTERISTICS
Parameter
Clock Cycle Time1
CL = 3
CL = 2
Clock to valid Output delay1,2
Output Data Hold Time2
Clock HIGH Pulse Width3
Clock LOW Pulse Width3
Input Setup Time3
Input Hold Time3
CLK to Output Low-Z2
CLK to Output High-Z
Row Active to Row Active Delay4
RAS to CAS Delay4
Row Precharge Time4
Row Active Time4
Row Cycle Time - Operation4
Row Cycle Time - Auto Refresh4,8
Last Data in to New Column Address Delay5
Last Data in to Row Precharge5
Last Data in to Burst Stop5
Column Address to Column Address Delay6
Number of Valid Output Data7
Symbol
tCC
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
tRRD
tRCD
tRP
tRAS
tRC
tRFC
tCDL
tRDL
tBDL
tCCD
125MHz
Min
Max
8
1000
10
1000
6
3
3
3
2
1
2
7
20
20
20
50
10,000
70
70
1
1
1
1.5
2
1
100MHz
Min
Max
10
1000
12
1000
7
3
3
3
2
1
2
7
20
20
20
50
10,000
80
80
1
1
1
1.5
2
2
83MHz
Min
Max
12
1000
15
1000
8
3
3
3
2
1
2
8
24
24
24
60
10,000
90
90
1
1
1
1.5
2
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
ea
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If tRISE of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the
next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self-refresh exit.
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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