AD8151(Rev0) 查看數據表（PDF） - Analog Devices
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AD8151 Datasheet PDF : 36 Pages
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AD8151
CS INPUT
UPDATE INPUT
WE INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
INPUT {DATA 1}
INPUT {DATA 2}
DISABLING
OUT[0:16][N:P]
OUTPUTS
INPUT {DATA 0}
tCSU
tUOT
tUOE
INPUT {DATA 1}
tUW
tWOT
tWOD
tCHU
tWHU
Figure 5. First Rank Write Cycle and Second Rank Update Cycle
Table V. First Rank Write Cycle and Second Rank Update Cycle
Symbol
Parameter
Conditions
Min
tCSU
tCHU
Setup Time
Hold Time
Chip Select to Update
Chip Select from Update
TA = 25°C
0
VDD = 5 V
0
tUOE
tWOE*
Output Enable Times
Update to Output Enable
Write Enable to Output Enable
VCC = 3.3 V
tUOT
tWOT
tUOD*
tWOD
Output Toggle Times
Output Disable Times
Update to Output Reprogram
Write Enable to Output Reprogram
Update to Output Disabled
Write Enable to Output Disabled
tWHU
Setup Time
Write Enable to Update
10
tUW
Width of Update Pulse
15
*Not Shown.
Typ
25
25
25
25
25
25
Max
40
40
30
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS INPUT
RE INPUT
A[4:0]
INPUTS
ADDR 1
ADDR 2
D[6:0]
OUTPUTS
tCSR
tRDE
DATA
{ADDR1}
tAA
DATA {ADDR2}
tRHA
tCHR
tRDD
Figure 6. Second Rank Readback Cycle
Table VI. Second Rank Readback Cycle
Symbol
tCSR
tCHR
tRHA
tRDE
tAA
tRDD
Setup Time
Hold Time
Enable Time
Access Time
Release Time
Parameter
Chip Select to Read Enable
Chip Select from Read Enable
Address from Read Enable
Data from Read Enable
Data from Address
Data from Read Enable
Conditions
Min Typ
TA = 25°C
0
VDD = 5 V
0
VCC = 3.3 V
5
10 kΩ
15
20 pF on D[6:0]
15
Bus
15
Max
30
Unit
ns
ns
ns
ns
ns
ns
–14–
REV. 0
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