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AD8151
(Rev.:Rev0)

33
17, 3.2 Gb/s Digital Crosspoint Switch

Analog Devices 

AD8151

matrix. It is useful to momentarily hold RESET at a logic LOW

state when powering up the AD8151 in a system that has mul-

tiple output signal pairs connected together. Failure to do this

may result in several signal outputs contending after power-up.

The reset pin is not gated by the state of the chip-select pin, CS.

It should be noted that the RESET pin does not program the

first rank, which will contain undefined data after power-up.

CONTROL INTERFACE TRANSLATORS

The AD8151 control interface has two supply pins, VDD and

VSS. The potential between the positive logic supply VDD and

the negative logic supply VSS must be at least 3 V and no more

than 5 V. Regardless of supply, the logic threshold is approxi-

mately 1.6 V above VSS, allowing the interface to be used with

most CMOS and TTL logic drivers.

The signal matrix supplies, VCC and VEE, can be set indepen-

dent of the voltage on VDD and VSS, with the constraints that

(VDD–VEE) ≤ 10 V. These constraints will allow operation of

the control interface on 3 V or 5 V while the signal matrix is

operated on +3.3 V or +5 V PECL, or –3.3 V or –5 V ECL.

CIRCUIT DESCRIPTION

The AD8151 is a high-speed 33 × 17 differential crosspoint switch

designed for data rates up to 3.2 Gb/s per channel. The AD8151

supports PECL-compatible input and output levels when operated

from a 5 V supply (VCC = 5 V, VEE = GND) or ECL-compatible

levels when operated from a –5 V supply (VCC = GND, VEE =

–5 V). To save power, the AD8151 can run from a +3.3 V supply

to interface with low-voltage PECL circuits or a –3.3 V supply

to interface with low-voltage ECL circuits. The AD8151 utilizes

differential current mode outputs with individual disable control,

which facilitates busing together the outputs of multiple AD8151s

to assemble larger switch arrays. This feature also reduces sys-

tem crosstalk and can greatly reduce power dissipation in a large

switch array. A single external resistor programs the current for

all enabled output stages, allowing for user control over output

levels with different output termination schemes and transmis-

sion line characteristic impedances.

High-Speed Data Inputs (INxxP, INxxN)

The AD8151 has 33 pairs of differential voltage-mode inputs.

The common-mode input range extends from the positive sup-

ply voltage (VCC) down to include standard ECL or PECL input

levels (VCC – 2 V). The minimum differential input voltage is

200 mV. Unused inputs may be connected directly to any level

within the allowed common-mode input range. A simplified

schematic of the input circuit is shown in Figure 9.

VCC

INxxP

INxxN

VEE

Figure 9. Simplified Input Circuit

In order to maintain signal fidelity at the high data rates supported

by the AD8151, the input transmission lines should be terminated

as close to the input pins as possible. The preferred input termi-

nation structure will depend primarily on the application and

the output circuit of the data source. Standard ECL compo-

nents have open emitter outputs that require pull-down resistors.

Three input termination networks suitable for this type of source

are shown in Figure 10. The characteristic impedance of the trans-

mission line is shown as ZO. The resistors, R1 and R2, in the

Thevenin termination are chosen to synthesize a VTT source

with an output resistance of ZO and an open-circuit output volt-

age equal to VCC – 2 V. The load resistors (RL) in the differential

termination scheme are needed to bias the emitter followers of

the ECL source.

VCC

ZO

INxxN

ZO

ECL SOURCE ZO

INxxP

ZO

VTT = VCC – 2V

(a)

VCC

VCC

VCC – 2V

ZO R1

R1

INxxN

ZO

R2

ECL SOURCE

INxxP

R2

VEE

(b)

ZO

ZO

RL

RL

ECL SOURCE

VEE

(c)

INxxN

2ZO

INxxP

Figure 10. AD8151 Input Termination from ECL/PECL

Sources: a) Parallel Termination Using VTT Supply, b)

Thevenin Equivalent Termination, c) Differential Termination

If the AD8151 is driven from a current mode output stage such

as another AD8151, the input termination should be chosen

to accommodate that type of source, as explained in the fol-

lowing section.

High-Speed Data Outputs (OUTyyP, OUTyyN)

The AD8151 has 17 pairs of differential current-mode outputs.

The output circuit, shown in Figure 11, is an open-collector

NPN current switch with resistor-programmable tail current and

output compliance extending from the positive supply voltage

(VCC) down to standard ECL or PECL output levels (VCC – 2 V).

The outputs may be disabled individually to permit outputs

from multiple AD8151s to be connected directly. Since the

output currents of multiple enabled output stages connected

in this way sum, care should be taken to ensure that the out-

put compliance limit is not exceeded at any time; this can be

achieved by disabling the active output driver before enabling

any inactive driver.

REV. 0

–17–

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