AD8151(Rev0) 查看數據表（PDF） - Analog Devices
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AD8151 Datasheet PDF : 36 Pages
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AD8151
Power Supplies
There are several options for the power supply voltages for the
AD8151, as there are two separate sections of the chip that require
power supplies. These are the control logic and the high-speed
data paths. Depending on the system architecture, the voltage
levels of these supplies can vary.
Logic Supplies
The control (programming) logic is CMOS and is designed to
interface with any of the various standard single-ended logic
families (CMOS or TTL). Its supply voltage pins are VDD (Pin
170, logic positive) and VSS (Pin 152, logic ground). In all cases
the logic ground should be connected to the system digital ground.
VDD should be supplied at between 3.3 V to 5 V to match the
supply voltage of the logic family that is used to drive the logic
inputs. VDD should be bypassed to ground with a 0.1 µF ceramic
capacitor. The absolute maximum voltage from VDD to VSS
is 5.5 V.
Data Path Supplies
The data path supplies have more options for their voltage lev-
els. The choices here will affect several other areas, like power
dissipation, bypassing, and common mode levels of the inputs
and outputs. The more positive voltage supply for the data paths
is VCC (Pins 41, 98, 149 and 171). The more negative supply is
VEE, which appears on many pins that will not be listed here.
The maximum allowable voltage across these supplies is 5.5 V.
The first choice in the data path power supplies is to decide
whether to run the device as ECL (Emitter-Coupled Logic) or
PECL (Positive ECL). For ECL operation, VCC will be at ground
potential, while VEE will be at a negative supply between –3.3 V
to –5 V. This will make the common-mode voltage of the inputs
and outputs at a negative voltage, see Figure 15.
+3.3V TO +5V
0.1F
VDD
AD8151
CONTROL
LOGIC
GND
VCC
DATA
PATHS
VSS
GND
VEE
0.1F
(ONE FOR EVERY TWO VEE PINS)
–3.3V TO –5V
Figure 15. Power Supplies and Bypassing for ECL
Operation
If the data paths are to be dc-coupled to other ECL logic devices
that run with ground as the most positive supply and a negative
voltage for VEE, then this is the proper way to run. However, if
the part is to be ac-coupled, it is not necessary to have the input/
output common mode at the same level as the other system
circuits, but it will probably be more convenient to use the same
supply rails for all devices.
For PECL operation, VEE will be at ground potential and VCC
will be a positive voltage from 3.3 V to 5 V. Thus, the common
mode of the inputs and outputs will be at a positive voltage.
These can then be dc-coupled to other PECL operated devices.
If the data paths are ac-coupled, then the common-mode levels
do not matter, see Figure 16.
+3.3V TO +5V
+3.3V TO +5V
0.1F
VDD
AD8151
CONTROL
LOGIC
0.1F
(ONE FOR EACH VCC PIN,
VCC
4 REQUIRED)
DATA
PATHS
VSS
VEE
GND
GND
Figure 16. Power Supplies and Bypassing for PECL
Operation
POWER DISSIPATION
For analysis, the power dissipation of the AD8151 can be divided
into three separate parts. These are the control logic, the data
path circuits and the (ECL or PECL) outputs, which are part of
the data path circuits, but can be dealt with separately. The first
of these, the control logic, is CMOS technology and does not
dissipate a significant amount of power. This power will, of
course, be greater when the logic supply is 5 V rather than 3 V,
but overall it is not a significant amount of power and can be
ignored for thermal analysis.
VDD
VCC
AD8151
CONTROL
LOGIC
DATA
PATHS
I, DATA PATH
LOGIC
VSS
VEE
IOUT
ROUT
VOUT LOW – VEE
GND
GND
Figure 17. Major Power Consumption Paths
The data path circuits operate between the supplies VCC and
VEE. As described in the power supply section, this voltage can
range from 3.3 V to 5 V. The current consumed by this section
will be constant, so operating at a lower voltage can save about
35 percent in power dissipation.
REV. 0
–19–
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