CY7C1328G(2012) 查看數據表（PDF） - Cypress Semiconductor

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CY7C1328G
(Rev.:2012)

4-Mbit (256 K × 18) Pipelined DCD Sync SRAM

Cypress Semiconductor 

CY7C1328G

Functional Block Diagram

A0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BWB

BWA

BWE

GW

CE1

CE2

CE3

OE

ADDRESS

REGISTER

2 A[1:0]

Q1

BURST

COUNTER AND

LOGIC

CLR

Q0

DQB, DQPB

BYTE

WRITE REGISTER

DQA , DQPA

BYTE

WRITE REGISTER

ENABLE

REGISTER

PIPELINED

ENABLE

ZZ

SLEEP

CONTROL

DQB , DQPB

BYTE

WRITE DRIVER

DQA, DQPA

BYTE

WRITE DRIVER

MEMORY

SENSE

AMPS

OUTPUT

REGISTERS

OUTPUT

BUFFERS

DQs,

DQPA

ARRAY

E

DQPB

INPUT

REGISTERS

Document Number: 38-05523 Rev. *J

Page 2 of 22

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