IDT70V24L20GI 查看數據表（PDF） - Integrated Device Technology
零件编号
产品描述 (功能)
比赛名单
IDT70V24L20GI Datasheet PDF : 22 Pages
| |||
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
ADDRESS
OE
CE or SEM (9)
tWC
tAW
tHZ (7)
CE or SEM (9)
R/W
DATAOUT
DATAIN
tAS (6)
(4)
tWP (2)
tWZ (7)
tDW
tWR (3)
tOW
tDH
(4)
2911 drw 08
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
ADDRESS
CE or SEM(9)
UB or LB(9)
tAS(6)
tWC
tAW
tEW (2)
tWR(3)
R/W
DATAIN
tDW
tDH
2911 drw 09
NOTES:
1. R/W or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output
Test Load (Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for
the entire tEW time.
61.412
Share Link: 