IDT70V24L20GI 查看數據表（PDF） - Integrated Device Technology

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IDT70V24L20GI

HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM

Timing Waveform of Slave Write (M/S = VIL)

Industrial and Commercial Temperature Ranges

tWP

R/W"A"

BUSY"B"

tWB(3)

tWH(1)

R/W"B"

(2)

NOTES:

1. tWH must be met for both BUSY input (slave) and output (master).

2. Busy is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the “slave” version.

2911 drw 13

Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)

ADDR"A"

and "B"

ADDRESSES MATCH

CE"A"

CE"B"

BUSY"B"

tAPS (2)

tBAC

tBDC

2911 drw 14

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing(1) (M/S = VIH)

ADDR"A"

ADDR"B"

BUSY"B"

tAPS (2)

ADDRESS "N"

MATCHING ADDRESS "N"

tBAA

tBDA

2911 drw 15

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

61.452

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