IDT70V24L20GI 查看數據表（PDF） - Integrated Device Technology
零件编号
产品描述 (功能)
比赛名单
IDT70V24L20GI Datasheet PDF : 22 Pages
| |||
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Oemperature and Supply Voltage Range(6)
70V24X15
Com'l Ony
70V24X20
Com'l
& Ind
70V24X25
Com'l
& Ind
Symbol
Parameter
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
tBDA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Access Time from Chip Enable LOW
tBDC
BUSY Disable Time from Chip Enable HIGH
tAPS
Arbitration Priority Set-up Time(2)
tBDD
BUSY Disable to Valid Data(3)
tWH
Write Hold After BUSY(5)
BUSY TIMING (M/S = VIL)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
Min.
Max.
Min.
Max.
Min.
Max. Unit
____
15
____
20
____
20
ns
____
15
____
20
____
20
ns
____
15
____
20
____
20
ns
____
15
____
17
____
17
ns
5
____
5
____
5
____
ns
____
18
____
30
____
30
ns
12
____
15
____
17
____
ns
0
____
12
____
0
____
15
____
0
____
ns
17
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
____
30
____
45
____
50
ns
____
25
____
35
____
35
ns
2911 tbl 13a
70V24X35
Com'l
& Ind
70V24X55
Com'l
& Ind
Symbol
Parameter
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
tBDA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Access Time from Chip Enable LOW
tBDC
BUSY Disable Time from Chip Enable HIGH
tAPS
Arbitration Priority Set-up Time(2)
tBDD
BUSY Disable to Valid Data(3)
tWH
Write Hold After BUSY(5)
BUSY TIMING (M/S = VIL)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
Min. Max. Min. Max. Unit
____
20
____
45
ns
____
20
____
40
ns
____
20
____
40
ns
____
20
____
35
ns
5
____
5
____
ns
____
35
____
40
ns
25
____
25
____
ns
0
____
0
____
ns
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
____
60
____
80
ns
____
45
____
65
ns
NOTES:
2911 tbl 13b
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform of Write
With Port-To-Port Delay (M/S = VIL)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part number indicates power rating (S or L).
61.432
Share Link: 