IDT70V24L20GI 查看數據表（PDF） - Integrated Device Technology

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IDT70V24L20GI

HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V24S/L

High-Speed 4K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

tSAA

tOH

A0-A2

SEM

I/O0

R/W

VALID ADDRESS

tAW

tWR

tEW

tDW

DATAIN

VALID

tAS

tWP

tDH

VALID ADDRESS

tACE

tSOP

DATAOUT

VALID(2)

tSWRD

OE

Write Cycle

NOTES:

1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).

2. “DATAOUT VALID” represents all I/O's (I/O0-I/O15)equal to the semaphore value.

Read Cycle

tAOE

2911 drw 10

Timing Waveform of Semaphore Write Contention(1,3,4)

A0"A"-A2"A"

MATCH

SIDE(2) "A"

R/W"A"

SEM"A"

A0"B"-A2"B"

SIDE(2) "B"

R/W"B"

tSPS

MATCH

SEM"B"

NOTES:

1. D0R = D0L = VIL, CER = CEL = VIH, or Both UB & LB = VIH.

2. All timing is the same for left or right port. “A” may be either left or right port. “B” is the opposite port from “A”.

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied there is no guarantee which side will be granted the semaphore flag.

2911 drw 11

61.422

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