LIS3L02DQ 查看數據表（PDF） - STMicroelectronics
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LIS3L02DQ Datasheet PDF : 19 Pages
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LIS3L02DQ
3.2 IC Interface
The complete measurement chain is composed by a low-noise capacitive amplifier which converts into an
analog voltage the capacitive unbalancing of the MEMS sensor and by three Σ∆ analog-to-digital convert-
ers, one for each axis, that translates the produced signal into a digital bitstream.
The Σ∆ converters are tigthly coupled with dedicated reconstruction filters which removes the high fre-
quency components of the quantization noise and provides low rate and high resolution digital words.
The charge amplifier and the Σ∆ converters are operated respectively at 107.5 KHz and 35.8 KHz.
The data rate at the output of the reconstruction depends on the user selected Decimation Factor (DF)
and span from 280 Hz to 4.48 KHz.
The acceleration data may be accessed through an I2C/SPI interface thus making the device particularly
suitable for direct interfacing with a microcontroller.
The LIS3L02DQ features a Data-Ready signal (DRY) which indicated when a new set of measured accel-
eration data is available thus simplifying data synchronization in digital system employing the device itself.
The LIS3L02DQ may also be configured to generate an inertial wake-up/interrupt signal when a program-
mable acceleration threshold is exceeded along one of the three axis.
3.3 Factory calibration
The IC interface is factory calibrated to provide to the final user a device ready to operate. The parameters
which are trimmed are: gain, offset, common mode and internal clock frequency.
The trimming values are stored inside the device by a non volatile structure. Any time the device is turned
on, the trimming parameters are downloaded into the registers to be employed during the normal opera-
tion thus allowing the final user to employ the device without any need for further calibration.
4 DIGITAL INTERFACES
The register embedded inside the LIS3L02DQ may be accessed through both the I2C and SPI serial in-
terfaces. The latter may be SW configured to operate either in SPI mode or in 3-wire interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS line must be
tied high (i.e connected to Vdd).
Table 5. Serial Interface Pin Description
PIN Name
PIN Description
CS
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
SCL/SPC
I2C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
SDA/SDI/SDO
I2C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SDO
SPI Serial Data Output (SDO)
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