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M37640E8FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

Ver 1.4

MITSUBISHI MICROCOMPUTERS

7640 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

1.19.1 UART Mode Register (UxMOD)

UxMOD defines data formats and selects the clock to

be used (see Figure 1.42).

1.19.2 UART Control Register (UxCON)

The UxCON specifies the initialization and enabling of a

transmit/receive process (see Figure 1.43). Data can

be read from and written to the Control Register.

MSB

7

LE1

LE0

PEN

PMD

STB

PS1

PS0

CLK

LSB

0

Address: 003016 ,003816

Access: R/W

Reset: 0016

CLK

PS1,0

STB

PMD

PEN

LE1,0

UART Clock Selection Bit (bit 0)

0: .

1: SCSGCLK

Internal Clock Prescaling Selection Bits (bits 2,1)

Bit 2

Bit 1

0

0: Division by 1

0

1: Division by 8

1

0: Division by 32

1

1: Division by 256

Stop Bits Selection Bit (bit 3)

0: 1

1: 2

Parity Selection Bit (bit 4)

0: Even

1: Odd

Parity Enable Bit (bit 5)

0: Off

1: On

Uart Character Length Selection Bits (bits 7,6)

Bit 7

Bit 6

0

0: 7 bits/character

0

1: 8 bits/character

1

0: 9 bits/character

1

1: Reserved

Fig. 1.42. UART Mode Register (U1MOD, U2MOD)

MSB

7

AME

RTS_SEL CTS_SEL

TIS

RIN

TIN

REN

TEN

LSB

0

Address: 003316 ,003B16

Access: R/W

Reset: 0016

TEN

REN

TIN

RIN

TIS

CTS_SEL

RTS_SEL

AME

Transmission Enable Bit (bit 0)

0: Disable the transmit process

1: Enable the transmit process. If the transmit process is disabled (TEN

cleared) during transmission, the transmit will not stop until completed.

Receive Enable Bit (bit 1)

0: Disable the receive process

1: Enable the receive process. If the receive process is disabled (REN

cleared) during reception, the receive will not stop until completed.

Transmission Initialization Bit (bit 2)

0: No action

1: Resets the UART transmit status register bits as well as stopping the

transmission operation. The TEN bit must be set and the transmit

buffer reloaded in order to transmit again. The TIN is automatically

reset one cycle after Tin is set.

Receive Initialization Bit (bit 3)

0: No action

1: Clears the UART receive status flags and the REN bit. If RIN is set

during receive in progress, receive operation is aborted. The RIN bit

is automatically reset one cycle after RIN is set.

Transmit Interrupt Source Selection Bit (bit 4)

0: Transmit interrupt occurs when the Transmit Buffer Empty flag is set.

1: Transmit interrupt occurs when the Transmit Complete flag is set.

Clear-to Send (CTS) Enable Bit (bit 5)

0: CTS function is disabled. P86 (or P82) is used as GPIO pin.

1: CTS function is enabled. P86 (or P82) is used as CTS input.

Request-to-Send (RTS) Enable Bit (bit 6)

0: RTS function is disabled, P87 (or P83) is used as GPIO pin.

1: RTS function is enabled, P87 (or p83) is used as RTS output.

UART Address Mode Enable Bit (bit 7)

0: Address Mode disabled

1: Address Mode enabled

Fig. 1.43. UART Control Register (U1CON, U2CON)

42

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