NJU3504FA1 查看數據表（PDF） - Japan Radio Corporation

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NJU3504FA1

4-BIT SINGLE CHIP MICRO CONTROLLER

Japan Radio Corporation  

NJU3504

An example of A/D conversion operation)

AIN2 terminal is selected and the result of the A/D conversion is transferred to RAM.

ADC_EXE

;

;

LP_ADC

;

ADC_END

;

ADC_DAT

:

:

SRPC

LDI

Y,0

CLA

TAP

;Peripheral register table 0

LDI

Y,7

LDI

A,%0010

TAP

LDI

A,%1010

TAP

;A/D control register

;AIN2 as the input

;Start of A/D conversion

; & AIN2 terminal

TPA

TBA

JMP

JMP

3

ADC_END

LP_ADC

;End of conversion ?

LDI

Y,8

;A/D conversion register

RRPC

;RAM to store the result of A/D conversion

LDI

X,ADC_DAT.X ;RAM address X=0

LDI

Y,ADC_DAT.Y ;RAM address Y=0

TPMICY

;The A/D converted data to RAM

; lower 4-bit at YLSB=0

TPMICY

;The A/D converted data to RAM

; higher 4-bit at YLSB=1

:

:

WSEG

;RAM area

DS

2

;Are for the result of A/D conversion

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