NJU3504FA1 查看數據表（PDF） - Japan Radio Corporation

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NJU3504FA1

4-BIT SINGLE CHIP MICRO CONTROLLER

Japan Radio Corporation  

NJU3504

s INTERNAL SYSTEM DESCRIPTION

The NJU3504 is a C-MOS 4-Bit Single Chip Micro Controller consisted of Original CPU Core, Selectable

Input-Output(I/O) Ports(MAX. 35 lines), Program ROM(4096 bytes), Data RAM(256 nibbles), 8-Bit A/D

Converter, 8-bit Serial Interface, Dual 8-Bit Timer/Counter, Interrupt Control Circuit and Oscillator Circuit.

The CPU block in the NJU3504 is consisted of ALU(Arithmetic Logic Unit) executing the binary adding,

subtracting or logical calculating, AC(Accumulator), four Registers, STACK allowing the 8-level subroutine-

nesting or Interrupt operation, Program Counter indicating 4096 addresses sequentially, and Timing generator.

The NJU3504 can be applied to the various markets because of the rich and efficient instruction set(59

instructions), wide operating voltage range(2.4V to 5.5V), low operating current, and STANDBY function

reducing the power supply current.

(1) INTERNAL REGISTER

• Accumulator(AC)

Accumulator(AC) is structured by the 4-bit register. It holds a data or a result of calculation, and

executes the shift-operation(ROTATE) or the data transference between the other registers and Data

Memory(RAM).

The accumulator condition is unknown on the “RESET” operation.

• X-register(X-reg)

X-register(X-reg) operates as the 4-bit register. X-reg operates also as the RAM address pointer with

Y-register.

The X-reg condition is unknown on the “RESET” operation.

• Y-register(Y-reg)

Y-register(Y-reg) operates as the 4-bit register or the RAM address pointer with X-reg.

The Y-reg condition is unknown on the “RESET” operation.

• X'-register(X'-reg)

X'-register(X’-reg) operates as the 4-bit register or a part of Program Memory(ROM) address pointer for

looking data in the ROM(TRM instruction) up function.

The X’-reg condition is unknown on the “RESET” operation.

• Y'-register(Y'-reg)

Y'-register(Y’-reg) operates as the 4-bit register or the peripheral register number(PHYn) pointer.

The Y’-reg condition is unknown on the “RESET” operation.

(2) INTERNAL FLAG

• RPC flag(RPC)

RPC flag(RPC) changes the instruction table. Several instructions perform either of the dual tasks in

accordance with the RPC flag condition. The RPC flag condition selects either of two couples of

registers which are X- and Y- reg, or X'- and Y'-reg. X- or Y- reg is selected when the RPC flag condition

is "0"(RPC=0). X'- or Y'- reg is selected when the RPC flag condition is "1"(RPC=1). The RPC flag

condition is set to "1"(RPC=1) by SRPC instruction, and is set to “0”(RPC=0) by RRPC instruction.

The RPC flag condition is set to “0” on the “RESET” operation.

• CARRY flag(CY)

When the carry occurs after the adding calculation, the CARRY flag(CY) condition is set to "1"(CY=1),

and when no carry, the CY flag condition is set to "0"(CY=0). When the borrow occurs after the

subtracting calculation, the CY flag condition is set to "0"(CY=0), and when no borrow, the CY flag

condition is set to "1"(CY=1). The bit-operation instruction operates the bit data rotation on the CY flag

combined with the accumulator or the other register.

The CY flag condition is set to "1"(CY=1) by SEC instruction and is set to "0"(CY=0) by CLC instruction.

The CY flag condition is kept until the end of the next instruction executing cycle. The CY flag condition is

unknown on the “RESET” operation.

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