NJU3504FA1 查看數據表（PDF） - Japan Radio Corporation

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NJU3504FA1

4-BIT SINGLE CHIP MICRO CONTROLLER

Japan Radio Corporation  

NJU3504

• PROGRAM COUNTER(PC)

PROGRAM COUNTER(PC) consisted of the 12-bit binary counter stores the address for the next

operating instruction in ROM. Data figures limited from b0 to b5 on the PC indicate the address in a page,

and data figures limited from b6 to b10 on the PC indicate the page in a bank, and data figure of MSB(b11)

on PC indicates a bank in ROM. Although the ROM address can be indicated 4096 addresses

continuously, the target address of JMP instruction is restricted by Paging structure in ROM. The target

address of JPL or CALL instruction is restricted by Banking structure in ROM.

The PC condition is set to “0” on the “RESET” operation.

(MSB) 11 10

9

8

7

6

5

4

3

2

1

0 (LSB)

Page allocation

Address location

MSB:Program Memory Bank allocation

JMP instruction can branch to the optional address in the page. The target address is indicated by the

data figures limited from b0 to b5(6 bits) on PC as shown in above. The paging structure can reduce the

program size in ROM and the JMP instruction execution time against JPL instruction because JMP

instruction is consisted of one byte(8 bits) length. JPL and CALL instructions can branch to the optional

address without considering the paging structure, because they consist of two bytes(16 bits) length

including the 11 bits of PC. But JPL and CALL instructions can not branch between the banks in ROM.

The memory bank register(PHY15) on the peripheral register table0 selects a bank in ROM. When the

branch target address is not found in the bank, the memory bank register requires to change the bank

number.

• STACK

STACK consists of three types of registers which are the 8 by 12 bits, the 5 by 4 bits, and the 2 by 1 bit

registers. The registers of STACK hold the data of PC automatically when the interrupt routine or the

subroutine is called. The 5 by 4 bits registers of STACK hold the data of the internal registers

automatically when the interrupt operation is executed. The 2 by 1 bit registers of STACK hold the data of

the internal flag automatically when the interrupt operation is executed. In the return (RET or RETI)

operation, PC, the internal registers, and the internal flags registers get the held data from STACK

automatically.

[For branch(CALL) and interrupt operation]

STACK POINTER 11

0

000

PC

001

PC

010

PC

011

PC

100

PC

101

PC

110

PC

111

PC

[For interrupt operation]

3

0

0

AC

X-register

RPC

X'-register

Y-register

Y'-register

0

STATUS

-9-

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