PDI1394P25BY 查看數據表（PDF） - Philips Electronics

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PDI1394P25BY

1-port 400 Mbps physical layer interface

Philips Electronics 

Philips Semiconductors

1-port 400 Mbps physical layer interface

Product data

PDI1394P25BY

7.0 FUNCTIONAL SPECIFICATION

The PDI1394P25 requires only an external 24.576 MHz crystal as a

reference. An external clock can be connected to XI instead of a

crystal. An internal oscillator drives an internal phase-locked loop

(PLL), which generates the required 393.216 MHz reference signal.

This reference signal is internally divided to provide the clock signals

used to control transmission of the outbound encoded Strobe and

Data information. A 49.152 MHz clock signal, supplied to the

associated LLC for synchronization of the two chips, is used for

resynchronization of the received data. The Power Down (PD)

function, when enabled by asserting the PD terminal high, stops

operation of the PLL and disables all circuits except the cable bias

detectors at the TPB terminals. The port transmitter circuitry and the

receiver circuitry are also disabled when the port is disabled,

suspended, or disconnected.

The PDI1394P25 supports an optional isolation barrier between

itself and its LLC. When the ISO input terminal is tied high, the

LLC interface outputs behave normally. When the ISO terminal is

tied low, internal differentiating logic is enabled, and the outputs are

driven such that they can be coupled through a capacitive or

transformer galvanic isolation barrier as described in IEEE 1394a

section 5.9.4. To operate with single capacitor (bus holder) isolation,

the ISO on the PHY terminal must be tied high. For more details on

using single capacitor isolation, please refer to the Philips Isolation

Application Note AN2452.

Data bits to be transmitted through the cable ports are received from

the LLC on two, four or eight parallel paths (depending on the

requested transmission speed). They are latched internally in the

PDI1394P25 in synchronization with the 49.152 MHz system clock.

These bits are combined serially, encoded, and transmitted at

98.304/196.608/393.216 Mbps (referred to as S100, S200, and

S400 speed, respectively) as the outbound data-strobe information

stream. During transmission, the encoded data information is

transmitted differentially on the TPB cable pair(s), and the encoded

strobe information is transmitted differentially on the TPA cable

pair(s).

During packet reception the TPA and TPB transmitters of the

receiving cable port are disabled, and the receivers for that port are

enabled. The encoded data information is received on the TPA cable

pair, and the encoded strobe information is received on the TPB

cable pair. The received data-strobe information is decoded to

recover the receive clock signal and the serial data bits. The serial

data bits are split into two-, four- or eight-bit parallel streams

(depending upon the indicated receive speed), resynchronized to

the local 49.152 MHz system clock and sent to the associated LLC.

Both the TPA and TPB cable interfaces incorporate differential

comparators to monitor the line states during initialization and

arbitration. The outputs of these comparators are used by the

internal logic to determine the arbitration status. The TPA channel

monitors the incoming cable common-mode voltage. The value of

this common-mode voltage is used during arbitration to set the

speed of the next packet transmission (speed signaling). In addition,

the TPB channel monitors the incoming cable common-mode

voltage on the TPB pair for the presence of the remotely supplied

twisted-pair bias voltage (cable bias detection).

The PDI1394P25 provides a 1.86 V nominal bias voltage at the

TPBIAS terminal for port termination. The PHY contains two

independent TPBIAS circuits. This bias voltage, when seen through

a cable by a remote receiver, indicates the presence of an active

connection. This bias voltage source must be stabilized by an

external filter capacitor of 0.3 µF–1 µF.

The line drivers in the PDI1394P25 operate in a high-impedance

current mode, and are designed to work with external 112 Ω

line-termination resistor networks in order to match the 110 Ω cable

impedance. One network is provided at each end of all twisted-pair

cable connections. Each network is composed of a pair of

series-connected 56 Ω resistors. The midpoint of the pair of resistors

that is directly connected to the twisted-pair A terminals is connected

to its corresponding TPBIAS voltage terminal. The midpoint of the pair

of resistors that is directly connected to the twisted-pair B terminals is

coupled to ground through a parallel R-C network with recommended

values of 5 kΩ and 220 pF. The values of the external line termination

resistors are designed to meet the standard specifications when

connected in parallel with the internal receiver circuits. An external

resistor connected between the R0 and R1 terminals sets the driver

output current, along with other internal operating currents. This

current setting resistor has a value of 6.34 kΩ ±1%.

When the power supply of the PDI1394P25 is removed while the

twisted-pair cables are connected, the PDI1394P25 transmitter and

receiver circuitry presents a high impedance to the cable in order to

not load the TPBIAS voltage on the other end of the cable.

The TEST0 terminal is used to set up various manufacturing test

conditions. For normal operation, it should be connected to ground.

The BRIDGE terminal is used to set the default value of the

Bridge_Aware bits i the Page 7 (Vendor Dependent) register. Tying

BRIDGE low directly (or through a 1 kΩ resistor to accommodate

other vendors’ pin-compatible chips), defaults the Bridge_Aware

field to “00” indicating a “non-bridge device.” Tying BRIDGE high,

defaults the Bridge_Aware bit to “11” indicating a “1394.1 bridge

compliant” device. Writing to the Bridge_Aware field overrides the

default setting from the BRIDGE terminal. The Bridge_Aware field is

reported in the self-ID packet at bit positions 18 and 19.

Four package terminals, used as inputs to set the default value for

four configuration status bits in the self-ID packet, should be

hard-wired high or low as a function of the equipment design. The

PC0–PC2 terminals are used to indicate the default power-class

status for the node (the need for power from the cable or the ability

to supply power to the cable). See Table 21 for power class

encoding. The C/LKON terminal is used as an input to indicate that

the node is a contender for bus manager.

The PHY supports suspend/resume as defined in the IEEE 1394a

specification. The suspend mechanism allows pairs of directly

connected ports to be placed into a low power state while

maintaining a port-to-port connection between 1394 bus segments.

While in a low power state, a port is unable to transmit or receive

data transaction packets. However, a port in a low power state is

capable of detecting connection status changes and detecting

incoming TPBIAS. When the PDI1394P25’s port is suspended, all

circuits except the bias-detection circuits are powered down,

resulting in significant power savings. The TPBIAS circuit monitors

the value of incoming TPA pair common-mode voltage when local

TPBIAS is inactive. Because this circuit has an internal current

source and the connected node has a current sink, the monitored

value indicates the cable connection status. This monitor is called

connect-detect.

2002 Oct 11

7

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