Philips Semiconductors
1-port 400 Mbps physical layer interface
Product data
PDI1394P25BY
9.0 RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITION
MIN
TYP MAX UNIT
VDD
VIH
VIL
IO
VID
VIC-100
Supply voltage
High-level input voltage, LREQ,
CTL0, CTL1, D0-D7
High-level input voltage,
C/LKON2, PC0–PC2, ISO, PD
RESET
Low-level input voltage, LREQ,
CTL0, CTL1, D0–D7
Low-level input voltage, C/LKON2,
PC0–PC2, ISO, PD,
RESET
Output current
Differential input voltage
amplitude
TPB common-mode input voltage
Source power node
Non-source power node
ISO = VDD, VDD >= 2.7 V
ISO = VDD, VDD >= 3.0 V
ISO = VDD
TPBIAS outputs
TPA, TPB cable inputs, during data reception
TPA, TPB cable inputs, during data arbitration
Speed signaling off
or S100 speed
signal
Source power node
Non-source power node
3.0
3.3
3.6
V
2.7 1
3.0
3.6
V
2.3
—
—
V
2.6
—
—
V
0.7 VDD —
0.6 VDD —
—
—
—
V
—
0.7
V
—
—
–6
118
168
1.165
1.165
— 0.2 VDD V
— 0.3 VDD —
—
2.5
mA
—
260
mV
—
265
mV
—
2.515
V
—
2.0151
V
VIC-200 TPB common-mode input voltage S200 speed signal
Source power node
Non-source power node
0.935
0.935
VIC-400 TPB common-mode input voltage S400 speed signal
Source power node
Non-source power node
0.523
0.523
tPU
Power-up reset time
Set by capacitor between RESET pin and GND
2
TPA, TPB cable inputs, S100 operation
—
Receive input jitter
TPA, TPB cable inputs, S200 operation
—
TPA, TPB cable inputs, S400 operation
—
Between TPA and TPB cable inputs, S100
operation
—
Receive input skew
Between TPA and TPB cable inputs, S200
operation
—
Between TPA and TPB cable inputs, S400
operation
—
fXTAL
Crystal or external clock
frequency
Crystal connected according to Figure 10 or
external clock input at pin XI
24.5735
NOTES:
1. For a node that does not source power to the bus (see Section 4.2.2.2 in the IEEE 1394-1995 standard).
2. C/LKON is only an input when RESET = 0.
—
—
—
—
—
—
—
—
—
—
—
24.576
2.515
2.0151
2.515
2.0151
—
1.08
0.5
0.315
0.8
0.55
0.5
24.5785
V
V
V
V
ms
ns
ns
ns
ns
ns
ns
MHz
2002 Oct 11
9