RTL8181 查看數據表（PDF） - Realtek Semiconductor
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RTL8181 Datasheet PDF : 50 Pages
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23
26-24
27
30-28
31
DISPCIB Disable PCI bridge,0 enabe PCI bridge,1
R/W
disable PCI bridge
WLANCKR Bus clock to WLAN clock ratio. 000=1:1,001= R/W
1:2,010=1:3,011=1:4,100=1:5,101=1:6,110=1:
7,111=1:8. The WLAN maximum clock is
40MHz.
WLANCKRE WLANCKR write enable
R/W
N
Reserved -
-
DISWLANB Disable WLAN, 0 enabe WLAN,1 disable R/W
WLAN
DPLL M,N parameter Register (PLLMN_REG)
The DPLL clock rate is setting by this equation:
44MHz*(M+1)/(N+1)
Bit Bit Name Description
R/W
4-0 NDIV
DPLL N parameter
R/W
7-5 Reserved -
-
13-8 MDIV
DPLL M parameter
R/W
14
MNEN
MDIV and NDIV write enable,0 disable ,1 R/W
enable
31-15 Reserved -
-
Memory parameterRegister (MEM _REG)
Bit Bit Name Description
R/W
2-0 MEMDIV MEM clock ,000:DPLL/1, 001: DPLL/1.5, R/W
010: DPLL/2,011:DPLL/2.5,
100:DPLL/3,101:DPLL/4, 110:DPLL/6,
111:DPLL/8
3
MEMDIVEN Enable MEMDIV writw,0 disable ,1 enable R/W
7-4 Reserved -
-
CPU parameter Register (CPU_REG)
Bit Bit Name Description
R/W
2-0 CPUDIV CPU clock ,000:DPLL/1, 001: DPLL/1.5, 010: R/W
DPLL/2,011:DPLL/2.5,
100:DPLL/3,101:DPLL/4, 110:DPLL/6,
111:DPLL/8
3
CPUDIVEN Enable CPUDIV writw,0 disable ,1 enable R/W
7-4 Reserved -
-
0
101
0
-
0
InitVal
00011
-
10011
0
0
InitVal
000
0
-
InitVal
000
0
-
RTL8181
6. Interrupt Controller
RTL8181 provides six hardware- interrupt inputs IRQ0-IRQ5 internally. Some devices will share the same IRQ signal.
Following table displays the IRQ map used by devices:
IRQ Number
0
1
2
3
4
5
Interrupt Source
Timer/Counter interrupt
GPIO/LBC interrupt
WLAN interrupt
UART/PCI interrupt
Ethernet0 interrupt
Ethernet1 interrupt
CONFIDENTIAL
17
v1.0
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