RTL8181 查看數據表（PDF） - Realtek Semiconductor
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RTL8181 Datasheet PDF : 50 Pages
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RTL8181
Besides, RTL8181could also supports two banks (F_CS0# and F_CS1#) access for flash memory. The system will always boot
up from bank 0. The boot bank is mapped to KSEG1 and its beginning physical address at 0xBFC0_0000 (physical address:
0x1FC0_0000). Bank 1 flash memory will be mapped to the address “0x1FC0_000 + flash size”. The flash size is configurable
from 1M to 8M bytes for each bank. If flash size set to 4M or 8M the 0xBFC0_0000 still map the first 4M bytes of flash.
There will have a new memory mapping from 0xBE00_0000. The 0xBE00_0000 mapped to the bank 0 byte 0.
Memory Conf iguration Register Set
Virtual address Size (byte) Name
Description
0xBD01_1000 4
MCR
Memory Configuration Register
0xBD01_1004 4
MTCR0 Memory Timing Configuration Register 0
0xBD01_1008 4
MTCR1 Memory Timing Configuration Register 1
Note: These three registers should be accessed in double word.
Memory Configuration Register (MCR)
Bit Bit Name Description
R/W
.31-30 FLSIZE
Flash size respective to one bank (byte).
R/W
00: 1M, 01: 2M, 10: 4M, 11:8M
29-28 SDRSIZE SDRAM size respective to one bank (bit).
R/W
00: 512Kx16x2, 01: 1Mx16x4, 10: 2Mx16x4, 11:Reserved
27 CAS
CAS Latency
WR
0: Latency=2, 1: Latency=3
26-25 FLBK0BW Flash bank 0 bus width.
R
01: 16 bit
24-23 FLBK1BW Flash bank 1 bus width
W/R
00 11 10: reserved, 01: 16 bit
22-21 -
Reserved
20 SDBUSWID SDRAM bus width
W/R
0: 16 bit, 1: 32 bit
19 MCK2LCK Memory clock mode.Power on latch from GPIOB[13].1:Memory clock R
is the same as CPU clock. 0:memory clock following the power on latch
from SYSCFG[3-0].
InitVal
11
01
0
01
1
0
18-16 BUSCLK
15-0 Reserved
Bus Clock to control auto-refresh timing
000:200, 001:100, 010:50, 011:25, 100:12.5, 101:6.25
110: 3.125, 111: 1.5625 MHz
Must be set to bit value 00.
Memory Timing Configuration Register 0 (MTCR0)
Bit Bit Name Description
31-28 CE0T_CS The timing interval between F_CE0# to WR#
Basic unit, 2*clock cycle
“0000” means 1 unit (2 clock cycles)
27-24 CE0T_WP The timing interval for WR# to be pulled-low
Basic unit, 2*clock cycle
“0000” means 1 unit (2 clock cycles)
23-20 CE1T_CS The timing interval between F_CE1# to WR#
Basic unit, 2*clock cycle
“0000” means 1 unit (2 clock cycles)
19-16 CE1T_WP The timing interval for WR# to be pulled-low
Basic unit, 2*clock cycle
“0000” means 1 unit (2 clock cycles)
15-0 -
Reserved
Note: The clock cycle is based memory clock.
Memory Timing Configuration Register 1 (MTCR1)
Bit Bit Name
Description
R/W 000
R/W 00
R/W InitVal
R/W 1111
R/W 1111
R/W 1111
R/W 1111
R/W InitVal
CONFIDENTIAL
19
v1.0
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