SAF-XC835MT-2FGI 查看數據表（PDF） - Infineon Technologies

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SAF-XC835MT-2FGI

8-Bit Single-Chip Microcontroller

Infineon Technologies 

XC835/836

Electrical Parameters

Table 10

ADC Characteristics (Operating Conditions apply; VDDP = 5 V;

fADCI <= 12 MHz) (cont’d)

Parameter

Symbol

Limit Values Unit Test

Min. Typ. Max.

Conditions /

Remarks

Total unadjusted

error

TUE3) CC –

– ±1

LSB8 8-bit conversion

with internal

reference4)

–

– +4/-2 LSB10 10-bit

conversion with

internal

reference4)5)

–

– +14/-2 LSB12 12-bit

conversion using

the Low Pass

Filter 4)

Differential

Nonlinearity

EADNL CC –

– +1.5/ -1 LSB 10-bit

conversion4)

Integral Nonlinearity EAINL CC –

– ±1.5 LSB 10-bit

conversion4)

Offset

EAOFF CC –

+4 –

LSB 10-bit

conversion4)

Gain

EAGAIN CC –

Switched

capacitance at an

analog input

CAINSW

Total capacitance at CAINT

an analog input

Input resistance of RAIN

an analog input

CC –

CC –

CC –

-4 –

23

– 12

1.5 2

LSB

pF

10-bit

conversion4)

4)6)

pF

4)6)

kΩ

4)

1) 1.2 V at VDDP = 3.0 V.

2) Not subject to production test, verified at CPU clock (fSCLK, CCLK ) = 8 MHz, TA = + 25 °C and VDDP = 5 V.

3) TUE is tested at VAREF = VDDP = 5.0 V and CPU clock (fSCLK, CCLK ) = 8 MHz.

4) Not subject to production test, verified by design/characterization.

5) If a reduced positive reference voltage is used, TUE will increase. If the positive reference is reduced by a

factor of K, the TUE will increased by 1/K. Example:K = 0.8, 1/K = 1.25; 1.25 X TUE = 2.5 LSB10.

6) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to

the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2.

Data Sheet

30

V1.2, 2011-03

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