SAF-XC835MT-2FGI 查看數據表（PDF） - Infineon Technologies

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SAF-XC835MT-2FGI

8-Bit Single-Chip Microcontroller

Infineon Technologies 

XC835/836

Electrical Parameters

3.2.4 Flash Memory Parameters

The XC835/836 is delivered with all Flash sectors erased (read all zeros).

The data retention time of the XC835/836’s Flash memory (i.e. the time after which

stored data can still be retrieved) depends on the number of times the Flash memory has

been erased and programmed.

Note: Flash memory parameters are not subject to production test but verified by design

and/or characterization.

Table 12 Flash Timing Parameters (Operating Conditions apply)

Parameter

Symbol

Limit Values Unit Remarks

Min. Typ. Max.

Read access time

tACC

(per byte)

CC – 125 – ns

Programming time tPR

(per wordline)

CC – 2.2 – ms

Erase time

tER

(one or more sectors)

CC – 120 – ms

Flash wait states

NWSFLASH CC

0

1

CPU clock = 8 MHz

CPU clock = 24 MHz

Table 13 Flash Data Retention and Endurance (Operating Conditions apply)

Retention

Endurance1)

Size

Remarks

20 years

1,000 cycles

up to 8 Kbytes

5 years

10,000 cycles

1 Kbyte

2 years

70,000 cycles

512 bytes

2 years

100,000 cycles

128 bytes

1) One cycle refers to the programming of all wordlines in a sector and erasing of sector. The Flash endurance

data specified in Table 13 is valid only if the following conditions are fulfilled:

- the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles.

- the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles.

- the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles.

Data Sheet

33

V1.2, 2011-03

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