MC92500ZQ 查看數據表（PDF） - Motorola => Freescale

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MC92500ZQ

ATM Cell Processor

Motorola => Freescale 

2.2.1 Ingress Cell Flow

In the Ingress direction, the MC92500 extracts cells

from the FIFO in the PHY. Cell discrimination based on

pre-defined header field values is performed to recog-

nize unassigned and invalid cells. Cell rate decoupling

is accomplished by discarding unassigned cells. Unas-

signed and invalid cell slots may be used to insert OAM

and messaging cells into the Ingress cell flow. For

VCCs, the 28-bit VPI/VCI address space (32-bit Link/

VPI/VCI if multiple physical links are supported) needs

to be compressed into a 16-bit Ingress Connection

Identifier (ICI). The MC92500 provides a choice of two

methods for performing VCC address compression to

obtain the ICI: a table lookup based on reduced ad-

dressing and an external address compression option.

For VPCs, the VPI field is used for a lookup into the

VP Table to obtain the ICI. The ICI is a pointer used to

access the context parameters for the current Ingress

cell from the external context memory. Included in

these parameters are cell counters, UPC/NPC traffic

descriptor, OAM parameters and switch parameters.

The UPC/NPC mechanism entails counting the arriving

cells and, using a flexible arrangement of traffic en-

forcement algorithms, admitting cells that do not violate

the traffic characteristics established for that connec-

tion. Violating cells are tallied and may optionally be

tagged or discarded (removed from the cell flow).

The OAM flags are used to control when and how OAM

cells are processed and to determine if the current user

cell belongs to a connection that has been selected for

a performance monitoring test. If the Ingress cell be-

longs to such a connection, the OAM table in external

memory contains the relevant parameters.

Subsequent to the context processing, the Ingress cells

are transferred to the Ingress switch interface. Option-

ally, the associated switch context parameters may be

added to the cell before the header or placed in the VPI/

VCI fields of the header.

Ingress Features

The Ingress section (Ingress refers to cells being trans-

ferred from the physical interface to the switch):

• Interfaces to one or more physical interface

chips via an 8-bit wide, parity-protected receive

data bus using the UTOPIA standard

• Decouples PHY timing from switch timing using

independent clocks and a FIFO in the physical

interface

• Performs Ingress cell discrimination based on

pre-assigned ATM cell header values

• Provides either a restricted address table

lookup scheme for Ingress address

compression or support for an external address

compression mechanism

• Reads Virtual Connection related UPC/NPC,

OAM and switch context parameters through a

32-bit wide interface to an external memory

• Provides per-connection usage count

• Provides per-connection option to copy cells to

the microprocessor

• Provides per-connection UPC/NPC policing

including detection/counting of violating cells

• Supports OAM continuity check, alarm

surveillance and loopback test on all

connections

• Provides OAM performance monitoring test

capabilities for selected connections

• Supports insertion of cells into the ingress cell

flow

• Optionally performs VPI/VCI translation

• Forwards the received ATM cells to the switch

using a UTOPIA-style interface, optionally

adding associated internal switch context

parameters

• Delay of 3 - 5 cell times from the PHY to the

switch

2.2.2 Egress Cell Flow

In the Egress direction, the MC92500 receives cells

from the switch along with their associated parameters,

if any. One of these parameters is the Egress Connec-

tion Identifier (ECI), which is used for direct lookup into

the context table located in external memory to obtain

the VPI/VCI, cell counters, and OAM flags. If multicast

translation is enabled, the Multicast Identifier (MI) is re-

ceived from the switch instead of the ECI, and the ECI

is found in the multicast translation table. Cells are sub-

ject to processing as indicated by the OAM flags. If the

Egress cell belongs to a connection that has been se-

lected for a performance monitoring test, the OAM Ta-

ble in external memory contains the relevant

parameters.

The Egress cell header is generated by inserting the

VPI/VCI-field obtained from the Address Translation

Table in the (GFC)/VPI/VCI position and modifying the

PTI-field if and when so indicated by the switch or in

case of an OAM cell. The cell is then forwarded to the

PHY I/F queue. Cell rate decoupling is performed in the

Egress direction, i.e. unassigned cells are optionally

generated if no cells are available from the switch.

MOTOROLA

6

MC92500

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