MC92500ZQ 查看數據表（PDF） - Motorola => Freescale

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MC92500ZQ

ATM Cell Processor

Motorola => Freescale 

2.4.6 Egress PHY Interface (EPHI)

The Egress PHY Interface (EPHI) block takes the pro-

cessed cells from the EPU, disassembles them into

bytes and transfers them to the physical layer using the

UTOPIA standard interface. Unassigned cells may be

inserted to provide cell rate decoupling.

2.4.7 External Memory Interface (EMIF)

The External Memory Interface (EMIF) block performs

address generation for the MC92500 accesses to the

external memory. It provides 32-bit data and 22-bit ad-

dress lines along with standard memory control signals.

2.4.8 Microprocessor Interface (MPIF)

The Microprocessor Interface (MPIF) block provides for

configuration of the MC92500, the transfer of cells be-

tween the microprocessor and the MC92500, and the

maintenance of external memory. A generic 68xxx -

compatible 32-bit slave interface is provided for easy

connection to a variety of microprocessor buses. Out-

put signals are provided that can serve as request sig-

nals for up to three DMA devices to improve system

performance.

A cell extraction queue is used to store cells that are di-

rected to the processor. Cells in this queue are trans-

ferred first to an internal cell buffer. Then they may be

read by the processor.

Cells to be inserted in the Ingress or Egress flows are

transferred from the processor memory to an internal

insertion queue.

2.4.9 Internal Scan (ISCAN)

The Internal Scan (ISCAN) block scans the external

memory for connections on which AIS, RDI, or Continu-

ity Check (CC) OAM cells must be inserted. When such

a connection is found, the cells are generated and add-

ed to the insertion queue for the cell flow in the appro-

priate direction.

2.4.10 Forward Monitoring Cell Generation

(FMC)

The Forward Monitoring Cell (FMC) Generation block

keeps track of the connections on which FMCs are

pending during the course of a Performance Monitoring

block test and maintains a priority among them. When

a hole in the cell flow is available, this block requests

the insertion of an FMC on the highest-priority connec-

tion.

3. REGISTERS DESCRIPTION

3.1 MC92500 Registers

The MC92500 registers are divided into several

groups. The register groups are:

Status Reporting Registers - these registers report on

the MC92500 status, and generally may be read and

written by the processor in either of the MC92500

modes of operation (Setup Mode or Operate Mode).

Control Registers - these registers control the

MC92500 operation, and may be read and written by

the processor in either of the MC92500 modes of oper-

ation (Setup Mode or Operate Mode).

Configuration Registers - these registers are used to

define the MC92500 configuration, and may be read by

the processor in either of the MC92500 modes of oper-

ation (Setup Mode or Operate Mode). These registers

may be written by the processor only in Setup Mode of

operation.

Cell Insertion Registers - these registers are used for

cell insertion into the MC92500 cell flow, and may be

written by the processor when the MC92500 is in Oper-

ate Mode. In order to improve performance, the

MC92500 Cell Insertion Registers receive special treat-

ment and may be accessed without wait states.

Cell Extraction Registers - these registers are used for

copying cells from the MC92500 cell flows, and may be

read by the processor when the MC92500 is in Operate

Mode. In order to improve performance, the MC92500

Cell Extraction Registers receive special treatment and

may be accessed without wait states.

Pseudo Registers - these registers are used to perform

certain operations on the MC92500, and may be written

by the processor in either of the MC92500 modes of op-

eration (Setup Mode or Operate Mode).

MC92500

MOTOROLA

9

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