MC92500ZQ 查看數據表（PDF） - Motorola => Freescale

零件编号

产品描述 (功能)

比赛名单

MC92500ZQ

ATM Cell Processor

Motorola => Freescale 

Egress Features

The Egress section (Egress refers to cells being trans-

ferred from the switch to the physical interface):

• Receives ATM cells and associated switch

context parameters (including congestion

notification) from the switch using a UTOPIA-

style interface

• Provides optional multicast identifier to

connection identifier translation

• Reads Egress context parameters from

external memory using direct lookup

• Provides per-connection usage count

• Provides per-connection option to copy cells to

the microprocessor

• Supports OAM continuity check, alarm

surveillance and loopback test on all

connections

• Provides OAM performance monitoring test

capabilities for selected connections

• Supports insertion of cells into the egress cell

flow

• Performs VPI/VCI translation

• Transfers ATM cells to one or more physical

interfaces via an 8-bit wide, parity-protected

transmit data bus using the UTOPIA standard

• Decouples PHY timing from switch timing using

independent clocks and a FIFO in the physical

interface

• Delay of 3 - 5 cell times from the switch to the

PHY

2.3 Other Functions

A general 32-bit slave system interface is provided for

configuration, control, status monitoring, and insertion

and extraction of cells. This interface provides for direct

register access to the MC92500.

The MC92500 is equipped with a standard IEEE

1149.1 boundary scan test logic.

2.4 MC92500 Block Diagram

Figure 4 contains a block diagram of the MC92500. The

individual blocks will be described in this section.

Utopia

I/F

Host

System

Utopia

I/F

Ingress PHY I/F (IPHI)

MultiPhy Support

Microprocessor I/F

(MPIF)

Cell Insertion

Cell Extraction

Configuration Regs.

Maintenance Access

Egress PHY I/F (EPHI)

MultiPhy Support

Ingress Cell Processor (IPU)

VP and VC Address compression

NPC/UPC

Cell Counting

OAM Operations

Add Switch parameters

Microprocessor Cell Insertion

Microprocessor Cell Extraction

Ingress Switch I/F

(ISWI)

Independent Clock

External Memory I/F

(EMIF)

Internal SCAN FMC Generation

(ISCAN)

(FMC)

JTAG

Boundary

Scan

Egress Cell Processor (EPU)

Multicast Translation

Cell Counting

OAM Operations

Address Translation

Microprocessor Cell Insertion

Microprocessor Cell Extraction

Egress Switch I/F

(ESWI)

Independent Clock

Extract Overhead

Utopia

I/F

Memory

I/F

Test

Port

Utopia

I/F

Figure 4. MC92500 Block Diagram

MC92500

MOTOROLA

7

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