MX10E8050X 查看數據表（PDF） - Macronix International

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MX10E8050X

Microcontroller

Macronix International 

Table. 7 TCON SFR (88H)

7

6

5

4

3

TF1

TR1

TF0

TR0

IE1

(MSB)

keep the above table with the following table

PRELIMINARY

MX10E8050I /

MX10E8050IA

2

1

0

IT1

IE0

IT0

(LSB)

Table. 8 Description of TCON bits

MNEMONIC POSITION

TF1

TCON.7

TR1

TCON.6

TF0

TCON.5

TR0

TCON.4

IE1

TCON.3

IT1

TCON.2

IE0

TOCN.1

IT0

TOCN.0

FUNCTION

Timer 1 overflow flag : set by hardware on Timer/Counter overflow. Cleared when

interrupt is processed.

Timer 1 control bit : set/cleared by software to turn Timer/counter ON/OFF.

Timer 0 overflow flag: set by hardware on Timer/Counter overflow. Cleared when

interrupt is processed.

Timer 0 control bit : set/cleared by software to turn Timer/counter ON/OFF.

Interrupt 1 edge flag: set by hardware when external interrupt is detected. Cleared

when interrupt is processed.

Interrupt 1 type control bit : set/cleared by software to specify falling edge/LOW

level triggered external interrupt.

Interrupt 0 edge flag: set by hardware when external interrupt is detected. Cleared

when interrupt is processed.

Interrupt 0 type control bit: set/cleared by software tospecify falling edge/LOW

level triggered external interrupt.

P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005

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