LF3370 查看數據表（PDF） - LOGIC Devices
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LF3370 Datasheet PDF : 24 Pages
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DEVICES INCORPORATED
LF3370
High-Definition Video Format Converter
output of the LUT section. The Gamma
LUT address can be chosen from any of
the 4 possible10-bit words that are
‘window’ selected from the13-bit Input
data bus. Configuring the desired LUT
address selector position is accomplished
by programming bits 10 & 9 of Configura-
tion Register 1. Once the LUT Select Data
position is programmed, it is meant to
control all three Gamma LUTs. Therefore,
the address selector positions of the three
LUTs cannot be independently controlled.
LUT loading is discussed in the LF
Interface™ section.
Rounding
The rounding circuitry found in the Matrix
Multiplier and Half-Band Filter sections
work in the same manner. The truncated
20 MSBs from the Matrix Multiplier or
Half-Band Filter output may be rounded
by being added to the contents of one of the
four Round Registers (see Figure 13). Each
round register is 20 bits wide and user-
programmable. This allows the Matrix
Multiplier’s or Half-Band Filter’s output to
be rounded to any precision required.
RSL1-0 determines which of the four
Round Registers are used in each Round-
ing Circuitry. A value of 00 on RSL1-0
selects Round Register 0. A value of 01
selects Round Register 1 and so on. RSL1-
0 may be changed every clock cycle if
desired. If rounding is not desired, the
user must load and select a Round
Register with value of 0. Round Register
loading is discussed in the LF Interface™
section.
Selecting
The selecting circuitry found in the Matrix
Multiplier and Half-Band Filter sections
work in the same manner. The output
word of the Matrix Multiplier and Half-
Band Filter feeding the RSL circuitry is the
20 MSBs. However, only 13 bits may be
sent to the next section. Therefore, the
Select Register determines which 13-bits
are passed. There are four select registers;
RSL1-0 determines which of the four Select
Registers are used in each Select Circuitry
(see Table 2). A value of 00 on RSL1-0
selects Select Register 0. A value of 01
selects Select Register 1 and so on. RSL1-0
may be changed every clock cycle if
desired. This allows the 13-bit window to
be changed every clock cycle. Select
Register loading is discussed in the
LF Interface™ section.
Limiting
The Limiting Circuitry found in the Matrix
Multiplier and Half-Band Filter sections
work in the same manner. The Limit
Registers determine the valid range of
output values for each of these two
sections. There are four 13-bit Limit
Registers for each section. RSL1-0 deter-
mines which of the four Limit Registers
are used in each Limiting Circuitry (see
Figure 13). A value of 00 on RSL1-0 selects
Limit Register 0. A value of 01 selects
Limit Register 1 and so on.
Each Limit Register contains an upper
and lower limit value. If the value fed to
the Limiting Circuitry is less than the
lower limit, the lower limit value is passed
as the Matrix Multiplier section’s or Half-
Band filter section’s output. If the value
fed to the Limiting Circuitry is greater
than the upper limit, the upper limit value
is passed as the Matrix Multiplier section’s
or Half-Band filter section’s output.
RSL1-0 may be changed every clock cycle if
desired thus allowing the limit range to be
changed every clock cycle. When loading
limit values into the device, the upper limit
must be greater than the lower limit. The
most negative and most positive values
you can load into the Limit Registers are
0FFFH and 1000H. Limit Register loading
is discussed in the LF Interface™ section.
LF Interface™
The LF Interface™ is used to load the
Configuration Registers, Matrix Multi-
plier/Key Scaler Coefficient Banks, Look-
Up Tables, Input/Output Bias registers,
RSL registers, HF0 and HF1 Count Values,
and Horizontal Blanking Levels.
TABLE 3.
TAP
1, 55
2, 54
3, 53
4, 52
5, 51
6, 50
7, 49
8, 48
9, 47
10, 46
11, 45
12, 44
13, 43
14, 42
15, 41
16, 40
17, 39
18, 38
19, 37
20, 36
21, 35
22, 34
23, 33
24, 32
25, 31
26, 30
27, 29
28 (center)
HALF-BAND FILTER IMPULSE RESPONSE
Impulse Response Out (Non-Interpolated Bit Weighing)
20-bit (MSB) Filter Out (HEX)
Decimal Equivalent
FFE35
0
002D2
0
FFB5C
0
00725
0
FF508
0
00F95
0
FEA10
0
01E59
0
FD6A8
0
0393E
0
FAF1B
0
0798D
0
F2BD2
0
28B30
401BC
–0.0008755
0
0.0013771
0
–0.00226593
0
0.0034885
0
–0.0053558
0
0.0076084
0
–0.01071167
0
0.0148182
0
–0.02018738
0
0.0279503
0
–0.0394993
0
0.05935097
0
–0.10360334
0
0.3179626
0.500846862
Video Imaging Products
12
03/13/2001–LDS.3370-F
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