LF3370 查看數據表（PDF） - LOGIC Devices
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LF3370 Datasheet PDF : 24 Pages
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DEVICES INCORPORATED
LF3370
High-Definition Video Format Converter
Register (0C00H). The HF1 Flag Count
Value is loaded in the same manner using
the appropriate address.
Table 32 shows an example of loading
Round/Select/Limit values. In this
example, Channel ‘A’ Matrix Multiplier
Register Set 0 (0E00H) is loaded with a 20-
bit Round value of 00020H, a 2-bit Select
value of 10H, a 13-bit Upper Limit value of
0FFFH, and a 13-bit Lower Limit value of
1001H. Other RSL registers are loaded in
the same manner using the appropriate
address.
Table 33 shows an example of loading a
Configuration Register. In this example,
Configuration Register 0 (0200H) is
loaded with 00AEH. This will setup the
Input Section to handle Luma on input
port A12-0 and interleaved Chroma on the
input port B12-0. The Output Section is
setup to output RGB on the output ports
W12-0, X12-0, Y12-0. The ‘functional
arrangement’ is setup in such a way that
the Half-Band Filter section is placed
before the Matrix Multiplier section. The
Half-Band Filters are setup for 1:2
interpolation and ‘normal order of
operations’ is selected.
Scaler Section, and Output Bias and feeds
the Output Multiplexer. Loading
Configuration Register 2 programs the
length of all four Core Bypass Delays (see
Table 7).
A LOW state detected on DATAPASS on
a rising edge of clock will output by-
passed data to the output port on the
following rising edge of CLK (see Figure
X). In addition, any of the four bypassed
channels can be passed to the ‘W’ output
channel during a ‘bypass’ event. For this
operation, use bits 7 and 8 of Configura-
tion Register 1 (see Table 6).
Half-Band Filter Bypass
At all times, while data is being fed into the
Half-Band Filter section, channels A, B, C,
and Key are fed into programmable length
delays. When the Half-Band Filter(s) are
set to filter bypass mode, that particular
channel passes through a programmable
delay and is not filtered. Since there are
only two Half-Band Filters in this section
found on channels B and C, channels A
and Key are always passed through their
respective programmable delays.
Please note, when using a single channel
video input or video output (interleaved
4:2:2), the Core Bypass Delay must be
TABLE 7. CONFIGURATION REGISTER 2 – ADDRESS 202H
BITS FUNCTION
DESCRIPTION
6-0
Core Bypass Delay Length Length of Core Bypass Delay Minus 2
12-7 Reserved
Must be Set to Zero
TABLE 8. CONFIGURATION REGISTER 3 – ADDRESS 203H
BITS FUNCTION
DESCRIPTION
6-0
Channel ‘A’ Filter Section Length of Filter Bypass Delay Minus 2
Bypass Delay Length
12-7 Reserved
Must be Set to Zero
BYPASS OPTIONS
Core Bypass
At all times during the normal operation
of the LF3370, video data on channels A,
B, C, and D are simultaneously being fed
from the output of the Input
Demultiplexer into the programmable
Core Bypass Delay (see Figure 15). This
allows users to switch between processed
video and unprocessed (bypassed) data
on-the-fly.
There is a separate Core Bypass Delay for
each channel. Each Core Bypass Delay
can be programmed for a length of 2 up to
129 CLK cycles for delay matching
between the bypass path and the core as
well as other operations. The Core Bypass
Delay bypasses the Input Bias, Input LUT,
Half-Band Filter, Matrix Multiplier/Key
TABLE 9. CONFIGURATION REGISTER 4 – ADDRESS 204H
BITS FUNCTION
DESCRIPTION
6-0
Channel ‘B’ Filter Section Length of Filter Bypass Delay Minus 2
Bypass Delay Length
12-7 Reserved
Must be Set to Zero
TABLE 10. CONFIGURATION REGISTER 5 – ADDRESS 205H
BITS FUNCTION
DESCRIPTION
6-0
Channel ‘C’ Filter Section Length of Filter Bypass Delay Minus 2
Bypass Delay Length
12-7 Reserved
Must be Set to Zero
TABLE 11. CONFIGURATION REGISTER 6 – ADDRESS 206H
BITS FUNCTION
DESCRIPTION
6-0
Key Channel Filter Section Length of Filter Bypass Delay Minus 2
Bypass Delay Length
12-7 Reserved
Must be Set to Zero
Video Imaging Products
15
03/13/2001–LDS.3370-F
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