WM8734 查看數據表（PDF） - Cirrus Logic
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WM8734 Datasheet PDF : 45 Pages
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WM8734
Production Data
Recommended values are C1 = 470nF (10V npo type), R1 = 47K, R2 = 100
C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so
protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing
abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can
have dramatic effects on the measured signal distortion at the output.
DEVICE OPERATION
DEVICE RESETTING
The WM8734 contains a power on reset circuit that resets the internal state of the device to a known
condition. The power on reset is applied as DCVDD powers on and released only after the voltage
level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on
threshold voltage then the power on reset is re-applied. The threshold voltages and associated
hysteresis are shown in the Electrical Characteristics table.
The user also has the ability to reset the device to a known state under software control as shown in
the table below.
REGISTER
ADDRESS
0001111
Reset Register
BIT
LABEL
8:0 RESET
Table 5 Software Control of Reset
DEFAULT
DESCRIPTION
not reset
Reset Register
Writing 00000000 to register resets
device
When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and
released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the
ACK signal (approximately 1 SCLK period, refer to Figure 24).
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. To allow WM8734 to be used in a centrally clocked system, the WM8734 is capable of
deriving the sample rate clock from this Master Clock (Master Mode) or receiving the sample rate
clock from an external source (Slave Mode).
CORE CLOCK
The WM8734 DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by
software as shown in Table 6 below.
REGISTER
ADDRESS
0001000
Sampling
Control
BIT
LABEL
6
CLKIDIV2
DEFAULT
0
Table 6 Software Control of Core Clock
DESCRIPTION
Core Clock divider select
1 = Core Clock is MCLK divided by 2
0 = Core Clock is MCLK
Having a programmable MCLK divider allows the device to be used in applications where higher
frequency master Clocks are available. For example the device can support 512fs master clocks
whilst fundamentally operating in a 256fs mode.
DIGITAL AUDIO INTERFACES
WM8734 may be operated in either one of the 4 offered audio interface modes. These are:
Right justified
Left justified
I2S
DSP mode
All four of these modes are MSB first and operate with data 16 to 32 bits, except right justified mode
which does not support 32 bits.
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PD, Rev 4.4, August 2013
20
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