WM8734 查看數據表（PDF） - Cirrus Logic
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WM8734 Datasheet PDF : 45 Pages
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WM8734
MPU INTERFACE TIMING
Production Data
CSB
SCLK
tCSL
tSCY
tSCH
tSCL
tCSH
tSCS
tCSS
SDIN
tDSU
tDHO
LSB
Figure 6 Program Register Input Timing – 3-Wire MPU Serial Control Mode
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
Program Register Input Information
SCLK rising edge to CSB rising
tSCS
edge
SCLK pulse cycle time
tSCY
SCLK pulse width low
tSCL
SCLK pulse width high
tSCH
SDIN to SCLK set-up time
tDSU
SCLK to SDIN hold time
tDHO
CSB pulse width low
tCSL
CSB pulse width high
tCSH
CSB rising to SCLK rising
tCSS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
60
ns
80
ns
20
ns
20
ns
20
ns
20
ns
20
ns
20
ns
20
ns
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PD, Rev 4.4, August 2013
12
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