EV-ADF4196SD1Z 查看數據表（PDF） - Analog Devices

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EV-ADF4196SD1Z

Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer

Analog Devices 

Data Sheet

DIFFERENTIAL AMPLIFIER

The internal, low noise, differential-to-single-ended amplifier

converts the differential charge pump output to a single-ended

control voltage for the tuning port of the VCO. Figure 26 shows

a simplified schematic of the differential amplifier. The output

voltage is equal to the differential voltage, offset by the voltage

on the CMR pin, according to the following equation:

VAOUT = (VAIN+ − VAIN−) + VCMR

(2)

The CMR offset voltage is internally biased to three-fifths of

VP3, the differential amplifier power supply voltage, as shown in

Figure 26. Connect a 0.1 µF capacitor to the ground plane from

the CMR pin to roll off the thermal noise of the biasing resistors.

AIN–

AIN+

500Ω

500Ω

500Ω

500Ω

AOUT

VP3

20kΩ CMR

30kΩ

C EXT =

0.1µF

Figure 26. Differential Amplifier Block Diagram

As shown in Figure 15, the differential amplifier output voltage

behaves according to Equation 2 over a 4 V range from ~1.2 V

minimum up to VP3 − 0.3 V maximum. However, fast settling

is guaranteed over a tuning voltage range from 1.8 V up to

VP3 − 0.8 V only. This range allows sufficient room for overshoot

in the PLL frequency settling transient.

Noise from the differential amplifier is suppressed inside the

PLL loop bandwidth. For loop bandwidths of >20 kHz, the 1/f

noise has a negligible effect on the PLL output phase noise.

Outside the loop bandwidth, the FM noise of the differential

amplifier modulates the VCO. The passive filter network following

the differential amplifier (see Figure 37) suppresses this noise

contribution to below the VCO noise from offsets of 400 kHz

and greater. This network has a negligible effect on lock time

because it is bypassed when SW3 is closed while the loop is

locking.

MUXOUT AND LOCK DETECT

MUXOUT Control

The output multiplexer on the ADF4196 allows the user to

access various internal points on the chip. The state of MUXOUT

is controlled by Bits[M4:M1] in the mux register. Figure 35

shows the full truth table; see Figure 27 for a block diagram

of the MUXOUT circuit.

ADF4196

LOGIC LOW

SERIAL DATA OUTPUT

R DIVIDER OUTPUT

N DIVIDER OUTPUT

THREE-STATE OUTPUT

TIMER OUTPUTS

DIGITAL LOCK DETECT

LOGIC HIGH

MUX

DVDD

CONTROL

MUXOUT

NOTE:

DGND

1. NOT ALL MUXOUT MODES THAT ARE SHOWN REFER TO THE

MUX REGISTER.

Figure 27. MUXOUT Circuit

Lock Detect

MUXOUT can be programmed to provide a digital lock detect

signal. Digital lock detect is active high. Its output goes high if

there are 40 successive PFD cycles with an input error of <3 ns.

For reliable lock detect operation with RF frequencies of <2 GHz,

it is recommended that this threshold be increased to 10 ns by

programming Register R6. The digital lock detect goes low again

when a new channel is programmed or when the error at the

PFD input exceeds 30 ns for one or more cycles.

INPUT SHIFT REGISTER

The ADF4196 serial interface includes a 24-bit input shift register.

Data is clocked in, MSB first, on each rising edge of CLK. Data

from the shift register is latched into one of eight control registers,

R0 to R7, on the rising edge of load enable (LE) The destination

register is determined by the state of the three control bits: C3

(DB2), C2 (DB1), and C1 (DB0) in the shift register. DB2, DB1,

and DB0 are the three LSBs, as shown in the timing diagram

in Figure 2. The truth table for these bits is shown in Table 6.

Figure 28 shows a summary of how the registers are programmed.

Table 6. C3, C2, and C1 Truth Table

Control Bits

C3 (DB2) C2 (DB1) C1 (DB0) Register Name

0

0

0

FRAC/INT

0

0

1

MOD/R

0

1

0

Phase

0

1

1

Function

1

0

0

Charge pump

1

0

1

Power-down

1

1

0

Mux

1

1

1

Test mode

Register

R0

R1

R2

R3

R4

R5

R6

R7

Rev. D | Page 13 of 28

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