EV-ADF4196SD1Z 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
比赛名单
EV-ADF4196SD1Z Datasheet PDF : 28 Pages
| |||
Data Sheet
ADF4196
CHARGE PUMP REGISTER (R4) LATCH MAP
RESERVED
9-BIT TIMEOUT COUNTER
TIMER
SELECT
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
1
C9 C8 C7 C6 C5 C4 C3 C2 C1 F2 F1 C3 (1) C2 (0) C1 (0)
F2 F1 TIMER SELECT
0 0 SW1/SW2
0 1 SW3
1 0 ICP
1 1 NOT USED
C9
C8
C7
C3
C2
0
0
0
.......... 0
0
0
0
0
.......... 0
0
0
0
0
.......... 0
1
0
0
0
.......... 0
1
.
.
.
.......... .
.
.
.
.
.......... .
.
.
.
.
.......... .
.
1
1
1
.......... 1
0
1
1
1
.......... 1
0
1
1
1
.......... 1
1
1
1
1
.......... 1
1
C1
TIMEOUT COUNTER xPFD CYCLES DELAY µs1
0
0
1
1
0
2
1
3
.
.
.
.
.
.
0
508
1
509
0
510
1
511
0
4
8
12
.
.
.
2032
2036
2040
2044
0
0.15
0.30
0.46
.
.
.
78.15
78.30
78.46
78.61
1DELAY WITH 26MHz PFD
Figure 33. Bit Map for Register R4
R4, the charge pump register, is used for programming the timers
for loop filter switches. These switches help maintain the stability
of the loop filter after boosting the charge pump current.
Control Bits
Register R4 is selected with C3, C2, and C1 (Bits[DB2:DB0]) set
to 1, 0, 0.
Reserved Bits
For normal operation, set the DB23 to DB14 reserved bits to
a hexadecimal code of 0x001.
9-Bit Timeout Counter
These bits are used to program the fast lock timeout counters.
The counters are clocked at one-quarter the PFD reference
frequency; therefore, their time delay scales with the PFD
frequency according to the following equation:
Timer Select
The two timer select bits select the timeout counter that is to
be programmed. Note that setting up the ADF4196 for correct
operation requires setup of these three timeout counters: ICP,
SW1/SW2, and SW3. Therefore, three writes to this register
are required in the initialization sequence. Table 7 shows
example values for a GSM Tx synthesizer with a 60 kHz final
loop bandwidth. See the Applications Information section for
more information.
Table 7. Recommended Values for a GSM Tx LO
Timer
Select
Timeout
Counter
Value
Time (µs) with
PFD = 13 MHz
10
ICP
28
8.6
01
SW3
35
10.8
00
SW1/SW2
35
10.8
Delay(s) = (Timeout Counter Value × 4)/(PFD Frequency)
For example, if 35 is loaded with timer select = 00, with
a 13 MHz PFD, SW1 and SW2 switch after the following:
(35 × 4)/13 MHz = 10.8 µs
On each write to R0, the timeout counters start. Switch SW3 closes
until the SW3 counter times out. Similarly, the SW1 and SW2
switches close until the SW1/SW2 counter times out. When the
ICP counter times out, the charge pump current is ramped down
from 64× to 1× in six binary steps. It is recommended that the
SW1/SW2 and SW3 timeout counter values be set equal to the
ICP timeout counter value plus 7, as in the example shown in
Table 7.
Rev. D | Page 19 of 28
Share Link: 